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soc/intel/apollolake: change LPDDR4 density enum definition

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Originally we use rank_density=0 to mean disable the channel, but actually
rank_density=0 means 4Gb density in the FSP.
This patch changes the LPDDR4 enum values to the real density number and
adds a switch statement to mapping the density define in the FSP.

BUG=b:178665760
BRANCH=NONE
TEST=build fw and flash to the dut, the dut can boot up successfully.

Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Chen 2021-06-03 11:10:57 +08:00 committed by Nick Vaccaro
parent 9f7e9cbc26
commit adda399234
2 changed files with 25 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/apollolake/include/soc/meminit.h
View File

@ -51,9 +51,9 @@ enum {
/* LPDDR4 module density in bits. */ /* LPDDR4 module density in bits. */
enum { enum {
LP4_8Gb_DENSITY = 2, LP4_8Gb_DENSITY = 8,
LP4_12Gb_DENSITY, LP4_12Gb_DENSITY = 12,
LP4_16Gb_DENSITY, LP4_16Gb_DENSITY = 16,
}; };
/* /*
@ -93,7 +93,7 @@ void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed);
* to the memory reference code. * to the memory reference code.
*/ */
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan, void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank, int rank_density_gb, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg); const struct lpddr4_swizzle_cfg *scfg);
struct lpddr4_sku { struct lpddr4_sku {

48
src/soc/intel/apollolake/meminit.c
View File

@ -19,24 +19,7 @@ static void accumulate_channel_memory(int density, int dual_rank)
/* For this platform LPDDR4 memory is 4 DRAM parts that are x32. 2 of /* For this platform LPDDR4 memory is 4 DRAM parts that are x32. 2 of
the parts are composed into a x64 memory channel. Thus there are 2 the parts are composed into a x64 memory channel. Thus there are 2
channels composed of 2 DRAMs. */ channels composed of 2 DRAMs. */
size_t sz; size_t sz = density;
/* Per rank density in Gb */
switch (density) {
case LP4_8Gb_DENSITY:
sz = 8;
break;
case LP4_12Gb_DENSITY:
sz = 12;
break;
case LP4_16Gb_DENSITY:
sz = 16;
break;
default:
printk(BIOS_ERR, "Invalid DRAM density: %d\n", density);
sz = 0;
break;
}
/* Two DRAMs per channel. */ /* Two DRAMs per channel. */
sz *= 2; sz *= 2;
@ -289,27 +272,38 @@ static void enable_logical_chan1(FSP_M_CONFIG *cfg,
} }
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan, void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank, int rank_density_gb, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg) const struct lpddr4_swizzle_cfg *scfg)
{ {
if (rank_density < LP4_8Gb_DENSITY || int fsp_rank_density;
rank_density > LP4_16Gb_DENSITY) {
printk(BIOS_ERR, "Invalid LPDDR4 density: %d\n", rank_density); switch (rank_density_gb) {
case LP4_8Gb_DENSITY:
fsp_rank_density = 2;
break;
case LP4_12Gb_DENSITY:
fsp_rank_density = 3;
break;
case LP4_16Gb_DENSITY:
fsp_rank_density = 4;
break;
default:
printk(BIOS_ERR, "Invalid LPDDR4 density: %d Gb\n", rank_density_gb);
return; return;
} }
switch (logical_chan) { switch (logical_chan) {
case LP4_LCH0: case LP4_LCH0:
enable_logical_chan0(cfg, rank_density, dual_rank, scfg); enable_logical_chan0(cfg, fsp_rank_density, dual_rank, scfg);
break; break;
case LP4_LCH1: case LP4_LCH1:
enable_logical_chan1(cfg, rank_density, dual_rank, scfg); enable_logical_chan1(cfg, fsp_rank_density, dual_rank, scfg);
break; break;
default: default:
printk(BIOS_ERR, "Invalid logical channel: %d\n", logical_chan); printk(BIOS_ERR, "Invalid logical channel: %d\n", logical_chan);
return; return;
} }
accumulate_channel_memory(rank_density, dual_rank); accumulate_channel_memory(rank_density_gb, dual_rank);
} }
void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
@ -330,7 +324,7 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
meminit_lpddr4(cfg, sku->speed); meminit_lpddr4(cfg, sku->speed);
if (sku->ch0_rank_density) { if (sku->ch0_rank_density) {
printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n", printk(BIOS_INFO, "LPDDR4 Ch0 density = %d Gb\n",
sku->ch0_rank_density); sku->ch0_rank_density);
meminit_lpddr4_enable_channel(cfg, LP4_LCH0, meminit_lpddr4_enable_channel(cfg, LP4_LCH0,
sku->ch0_rank_density, sku->ch0_rank_density,
@ -339,7 +333,7 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
} }
if (sku->ch1_rank_density) { if (sku->ch1_rank_density) {
printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n", printk(BIOS_INFO, "LPDDR4 Ch1 density = %d Gb\n",
sku->ch1_rank_density); sku->ch1_rank_density);
meminit_lpddr4_enable_channel(cfg, LP4_LCH1, meminit_lpddr4_enable_channel(cfg, LP4_LCH1,
sku->ch1_rank_density, sku->ch1_rank_density,