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mb/google/volteer/var/terrador: change GPP_B2 to PLTRST

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Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang.
Add GPP_B2 to the early_gpio_table.

BUG=b:174776411
BRANCH=none
TEST=none

Change-Id: I1214246bb1318869e9b6f57cb6a7e74bbe6574cc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Nick Vaccaro
2021-06-11 18:03:51 -07:00
parent 11d6741e79
commit ae10d8119e
1 changed files with 6 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/volteer/variants/terrador/gpio.c
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@@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */
@@ -184,11 +184,6 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* C8 : UART0 RX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART0 TX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
@@ -198,7 +193,7 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
@@ -212,6 +207,10 @@ static const struct pad_config early_gpio_table[] = {
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C8 : UART0 RX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART0 TX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */