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AGESA vendorcode: Suppress maybe-uninitialized warnings

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Compiling libagesa with -O2 would throws error on these.

Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14413
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2016-04-19 07:17:35 +03:00
parent 4dcbdb0ab9
commit ae29635876
6 changed files with 42 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -150,7 +150,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -399,7 +399,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -477,8 +477,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -586,7 +586,7 @@ MemTAutoCycTiming3 (
SPD_TFAW
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT16 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -712,7 +712,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -909,7 +909,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;

14
src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -153,7 +153,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -437,7 +437,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -517,8 +517,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -638,7 +638,7 @@ MemTAutoCycTiming3 (
0
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -764,7 +764,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -974,7 +974,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;

14
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -155,7 +155,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -434,7 +434,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -514,8 +514,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -635,7 +635,7 @@ MemTAutoCycTiming3 (
0
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -761,7 +761,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -971,7 +971,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;

14
src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -154,7 +154,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -461,7 +461,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -541,8 +541,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -662,7 +662,7 @@ MemTAutoCycTiming3 (
0
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -788,7 +788,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -1009,7 +1009,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;

14
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -153,7 +153,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -462,7 +462,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -544,8 +544,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -665,7 +665,7 @@ MemTAutoCycTiming3 (
0
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -791,7 +791,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -1012,7 +1012,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;

14
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
View File

@@ -153,7 +153,7 @@ MemTDIMMPresence3 (
UINT8 Channel;
UINT8 i;
MEM_PARAMETER_STRUCT *RefPtr;
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
@@ -470,7 +470,7 @@ MemTSPDGetTargetSpeed3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 Dimm;
UINT8 Dct;
UINT8 Channel;
@@ -552,8 +552,8 @@ MemTSPDCalcWidth3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferAPtr;
UINT8 *SpdBufferBPtr;
UINT8 *SpdBufferAPtr = NULL;
UINT8 *SpdBufferBPtr = NULL;
MEM_NB_BLOCK *NBPtr;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
@@ -673,7 +673,7 @@ MemTAutoCycTiming3 (
0
};
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
UINT8 MiniMaxTrfc[4];
@@ -799,7 +799,7 @@ MemTSPDSetBanks3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 i;
UINT8 ChipSel;
UINT8 DimmID;
@@ -1020,7 +1020,7 @@ MemTSPDGetTCL3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT8 *SpdBufferPtr;
UINT8 *SpdBufferPtr = NULL;
UINT8 CLdesired;
UINT8 CLactual;
UINT8 Dimm;