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inteltool: Add support for Haswell ULT and Lynx Point LP

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Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
Reviewed-on: http://review.coreboot.org/7275
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Dennis Wassenberg
2014-10-30 10:30:40 +01:00
committed by Nico Huber
parent 51a2d0e461
commit ae6685fe4f
7 changed files with 171 additions and 1 deletions
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67
util/inteltool/pcie.c
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@@ -118,6 +118,63 @@ static const io_register_t sandybridge_dmi_registers[] = {
/* ... - Reserved */
};
/*
* All Haswell DMI Registers per
*
* Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family,
* and Mobile Intel Celeron Processor Family
* Datasheet Volume 2
* 329002-002
*/
static const io_register_t haswell_ult_dmi_registers[] = {
{ 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
{ 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
{ 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
{ 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
/* { 0x0E, 2, "RSVD" }, // Reserved */
{ 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
{ 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
/* { 0x18, 2, "RSVD" }, // Reserved */
{ 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
{ 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
{ 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
/* { 0x24, 2, "RSVD" }, // Reserved */
{ 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
{ 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
{ 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
/* { 0x30, 2, "RSVD" }, // Reserved */
{ 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
{ 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
{ 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
/* { 0x3C, 2, "RSVD" }, // Reserved */
{ 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
{ 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
{ 0x44, 4, "DMIESD" }, // DMI Element Self Description
/* { 0x48, 4, "RSVD" }, // Reserved */
/* { 0x4C, 4, "RSVD" }, // Reserved */
{ 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
/* { 0x54, 4, "RSVD" }, // Reserved */
{ 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
{ 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
{ 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
/* { 0x64, 4, "RSVD" }, // Reserved */
{ 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
/* { 0x6C, 4, "RSVD" }, // Reserved */
/* { 0x70, 4, "RSVD" }, // Reserved */
/* { 0x74, 4, "RSVD" }, // Reserved */
/* { 0x78, 4, "RSVD" }, // Reserved */
/* { 0x7C, 4, "RSVD" }, // Reserved */
/* { 0x80, 4, "RSVD" }, // Reserved */
/* { 0x84, 4, "RSVD" }, // Reserved */
{ 0x88, 2, "LCTL" }, // Link Control
/* ... - Reserved */
{ 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
{ 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
{ 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
{ 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
/* ... - Reserved */
};
/*
* Egress Port Root Complex MMIO configuration space
*/
@@ -148,6 +205,7 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
@@ -247,6 +305,14 @@ int print_dmibar(struct pci_dev *nb)
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
dmi_registers = haswell_ult_dmi_registers;
size = ARRAY_SIZE(haswell_ult_dmi_registers);
dmibar_phys = pci_read_long(nb, 0x68);
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
default:
printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
return 1;
@@ -326,6 +392,7 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;