cpu/x86: Support CPUs without rdmsr/wrmsr instructions

Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2016-07-24 08:03:37 -07:00
parent 7c2e5396a3
commit ae738acdc5
13 changed files with 148 additions and 128 deletions

View File

@@ -87,7 +87,7 @@
* +0: Number of variable MTRRs to clear
*/
#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
push %esp
call soc_set_mtrrs
@@ -136,7 +136,7 @@
dec %ebx
jmp 2b
2:
#endif /* CONFIG_SOC_SETS_MTRRS */
#endif /* CONFIG_SOC_SETS_MSRS */
post_code(0x39)
@@ -147,7 +147,7 @@
post_code(0x3a)
#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
call soc_enable_mtrrs
#else
/* Enable MTRR. */
@@ -155,7 +155,7 @@
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
#endif /* CONFIG_SOC_SETS_MTRRS */
#endif /* CONFIG_SOC_SETS_MSRS */
post_code(0x3b)

View File

@@ -88,11 +88,4 @@ void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd);
void soc_pre_ram_init(struct romstage_params *params);
/*
* Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
* Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
*/
asmlinkage void *soc_set_mtrrs(void *top_of_stack);
asmlinkage void soc_enable_mtrrs(void);
#endif /* _COMMON_ROMSTAGE_H_ */