cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@@ -87,7 +87,7 @@
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* +0: Number of variable MTRRs to clear
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*/
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#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
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#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
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push %esp
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call soc_set_mtrrs
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@@ -136,7 +136,7 @@
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dec %ebx
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jmp 2b
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2:
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#endif /* CONFIG_SOC_SETS_MTRRS */
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#endif /* CONFIG_SOC_SETS_MSRS */
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post_code(0x39)
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@@ -147,7 +147,7 @@
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post_code(0x3a)
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#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
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#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
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call soc_enable_mtrrs
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#else
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/* Enable MTRR. */
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@@ -155,7 +155,7 @@
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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#endif /* CONFIG_SOC_SETS_MTRRS */
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#endif /* CONFIG_SOC_SETS_MSRS */
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post_code(0x3b)
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@@ -88,11 +88,4 @@ void soc_memory_init_params(struct romstage_params *params,
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MEMORY_INIT_UPD *upd);
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void soc_pre_ram_init(struct romstage_params *params);
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/*
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* Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
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* Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
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*/
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asmlinkage void *soc_set_mtrrs(void *top_of_stack);
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asmlinkage void soc_enable_mtrrs(void);
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#endif /* _COMMON_ROMSTAGE_H_ */
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