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cpu/x86: Support CPUs without rdmsr/wrmsr instructions

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Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2016-07-24 08:03:37 -07:00
parent 7c2e5396a3
commit ae738acdc5
13 changed files with 148 additions and 128 deletions
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21
src/include/cpu/x86/msr.h
View File

@ -29,6 +29,23 @@ typedef struct msrinit_struct
msr_t msr;
} msrinit_t;
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
msr_t soc_msr_read(unsigned index);
void soc_msr_write(unsigned index, msr_t msr);
/* Handle MSR references in the other source code */
static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
{
return soc_msr_read(index);
}
static inline __attribute__((always_inline)) void wrmsr(unsigned index,
msr_t msr)
{
soc_msr_write(index, msr);
}
#else /* CONFIG_SOC_SETS_MSRS */
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* ram, the cache as ram stack can no longer be used. Called
@ -50,7 +67,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
return result;
}
static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
static inline __attribute__((always_inline)) void wrmsr(unsigned index,
msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
@ -59,6 +77,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms
);
}
#endif /* CONFIG_SOC_SETS_MSRS */
#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */

13
src/include/cpu/x86/mtrr.h
View File

@ -124,4 +124,17 @@ int get_free_var_mtrr(void);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
#if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \
&& !defined(__ROMCC__))
#include <cpu/x86/msr.h>
#include <arch/cpu.h>
/*
* Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
* Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
*/
asmlinkage void *soc_set_mtrrs(void *top_of_stack);
asmlinkage void soc_enable_mtrrs(void);
#endif /* CONFIG_SOC_SETS_MSRS ... */
#endif /* CPU_X86_MTRR_H */