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cpu/x86: Support CPUs without rdmsr/wrmsr instructions

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Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2016-07-24 08:03:37 -07:00
parent 7c2e5396a3
commit ae738acdc5
13 changed files with 148 additions and 128 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/quark/Kconfig
View File

@@ -30,7 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select C_ENVIRONMENT_BOOTBLOCK
select REG_SCRIPT
select SOC_INTEL_COMMON
select SOC_SETS_MTRRS
select SOC_SETS_MSRS
select TSC_CONSTANT_RATE
select UART_OVERRIDE_REFCLK
select UDELAY_TSC

3
src/soc/intel/quark/include/soc/reg_access.h
View File

@@ -19,6 +19,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <delay.h>
#include <fsp/util.h>
#include <reg_script.h>
@@ -230,6 +231,8 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
uint32_t port_reg_read(uint8_t port, uint32_t offset);
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
uint32_t reg_host_bridge_unit_read(uint32_t reg_address);
uint32_t reg_legacy_gpio_read(uint32_t reg_address);
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);

2
src/soc/intel/quark/include/soc/romstage.h
View File

@@ -26,8 +26,6 @@
#include <soc/reg_access.h>
asmlinkage void *car_state_c_entry(void);
uint32_t port_reg_read(uint8_t port, uint32_t offset);
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
void report_platform_info(void);
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
void pcie_init(void);

88
src/soc/intel/quark/reg_access.c
View File

@@ -15,6 +15,7 @@
#define __SIMPLE_DEVICE__
#include <cpu/x86/mtrr.h>
#include <console/console.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -71,6 +72,33 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address)
return (uint16_t)(gpio_base_address + reg_address);
}
static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
{
uint32_t offset;
/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
if (index == MTRR_CAP_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
else if (index == MTRR_DEF_TYPE_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
else if (index == MTRR_FIX_64K_00000)
offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
offset = ((index - MTRR_FIX_16K_80000) << 1)
+ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
offset = ((index - MTRR_FIX_4K_C0000) << 1)
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
offset = (index - MTRR_PHYS_BASE(0))
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
else {
printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
die("Invalid MTRR index specified!\n");
}
return offset;
}
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
{
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
@@ -96,6 +124,22 @@ void mea_write(uint32_t reg_address)
& QNC_MEA_MASK);
}
uint32_t port_reg_read(uint8_t port, uint32_t offset)
{
/* Read the port register */
mea_write(offset);
mcr_write(QUARK_OPCODE_READ, port, offset);
return mdr_read();
}
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
{
/* Write the port register */
mea_write(offset);
mdr_write(value);
mcr_write(QUARK_OPCODE_WRITE, port, offset);
}
static uint32_t reg_gpe0_read(uint32_t reg_address)
{
/* Read the GPE0 register */
@@ -348,6 +392,50 @@ static void reg_write(struct reg_script_context *ctx)
}
}
msr_t soc_msr_read(unsigned index)
{
uint32_t offset;
union {
uint64_t u64;
msr_t msr;
} value;
/* Read the low 32-bits of the register */
offset = mtrr_index_to_host_bridge_register_offset(index);
value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
/* For 64-bit registers, read the upper 32-bits */
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
offset += 1;
value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
offset);
}
return value.msr;
}
void soc_msr_write(unsigned index, msr_t msr)
{
uint32_t offset;
union {
uint32_t u32[2];
msr_t msr;
} value;
/* Write the low 32-bits of the register */
value.msr = msr;
offset = mtrr_index_to_host_bridge_register_offset(index);
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]);
/* For 64-bit registers, write the upper 32-bits */
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
offset += 1;
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
value.u32[1]);
}
}
const struct reg_script_bus_entry soc_reg_script_bus_table = {
SOC_TYPE, reg_read, reg_write
};

97
src/soc/intel/quark/romstage/mtrr.c
View File

@@ -21,93 +21,6 @@
#include <soc/pci_devs.h>
#include <soc/romstage.h>
static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
{
uint32_t offset;
/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
if (index == MTRR_CAP_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
else if (index == MTRR_DEF_TYPE_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
else if (index == MTRR_FIX_64K_00000)
offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
offset = ((index - MTRR_FIX_16K_80000) << 1)
+ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
offset = ((index - MTRR_FIX_4K_C0000) << 1)
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
offset = (index - MTRR_PHYS_BASE(0))
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
else {
printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
die("Invalid MTRR index specified!\n");
}
return offset;
}
uint32_t port_reg_read(uint8_t port, uint32_t offset)
{
/* Read the port register */
mea_write(offset);
mcr_write(QUARK_OPCODE_READ, port, offset);
return mdr_read();
}
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
{
/* Write the port register */
mea_write(offset);
mdr_write(value);
mcr_write(QUARK_OPCODE_WRITE, port, offset);
}
msr_t soc_mtrr_read(unsigned long index)
{
uint32_t offset;
union {
uint64_t u64;
msr_t msr;
} value;
/* Read the low 32-bits of the register */
offset = mtrr_index_to_host_bridge_register_offset(index);
value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
/* For 64-bit registers, read the upper 32-bits */
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
offset += 1;
value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
offset);
}
return value.msr;
}
void soc_mtrr_write(unsigned long index, msr_t msr)
{
uint32_t offset;
union {
uint32_t u32[2];
msr_t msr;
} value;
/* Write the low 32-bits of the register */
value.msr = msr;
offset = mtrr_index_to_host_bridge_register_offset(index);
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]);
/* For 64-bit registers, write the upper 32-bits */
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
offset += 1;
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
value.u32[1]);
}
}
asmlinkage void *soc_set_mtrrs(void *top_of_stack)
{
union {
@@ -150,7 +63,7 @@ asmlinkage void *soc_set_mtrrs(void *top_of_stack)
mtrr_count = (*mtrr_data++) * 2;
data.u64 = 0;
while (mtrr_count-- > 0)
soc_mtrr_write(mtrr_reg++, data.msr);
soc_msr_write(mtrr_reg++, data.msr);
/* Setup the specified variable MTRRs */
mtrr_reg = MTRR_PHYS_BASE(0);
@@ -158,10 +71,10 @@ asmlinkage void *soc_set_mtrrs(void *top_of_stack)
while (mtrr_count-- > 0) {
data.u32[0] = *mtrr_data++;
data.u32[1] = *mtrr_data++;
soc_mtrr_write(mtrr_reg++, data.msr); /* Base */
soc_msr_write(mtrr_reg++, data.msr); /* Base */
data.u32[0] = *mtrr_data++;
data.u32[1] = *mtrr_data++;
soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */
soc_msr_write(mtrr_reg++, data.msr); /* Mask */
}
/* Remove setup_stack_and_mtrrs data and return the new top_of_stack */
@@ -178,7 +91,7 @@ asmlinkage void soc_enable_mtrrs(void)
} data;
/* Enable MTRR. */
data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
data.msr = soc_msr_read(MTRR_DEF_TYPE_MSR);
data.u32[0] |= MTRR_DEF_TYPE_EN;
soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr);
soc_msr_write(MTRR_DEF_TYPE_MSR, data.msr);
}