cpu/x86: Support CPUs without rdmsr/wrmsr instructions

Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/quark/include/soc/reg_access.h

@@ -19,6 +19,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <cpu/x86/msr.h>
 #include <delay.h>
 #include <fsp/util.h>
 #include <reg_script.h>
@@ -230,6 +231,8 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
 uint32_t mdr_read(void);
 void mdr_write(uint32_t value);
 void mea_write(uint32_t reg_address);
+uint32_t port_reg_read(uint8_t port, uint32_t offset);
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 uint32_t reg_host_bridge_unit_read(uint32_t reg_address);
 uint32_t reg_legacy_gpio_read(uint32_t reg_address);
 void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);

src/soc/intel/quark/include/soc/romstage.h

@@ -26,8 +26,6 @@
 #include <soc/reg_access.h>
 
 asmlinkage void *car_state_c_entry(void);
-uint32_t port_reg_read(uint8_t port, uint32_t offset);
-void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 void report_platform_info(void);
 int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
 void pcie_init(void);