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soc/intel/cannonlake: Add Acoustic features

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Expose the following FSP UPD interface into coreboot, which is the
following:
AcousticNoiseMitigation
FastPkgCRampDisableIa
FastPkgCRampDisableGt
FastPkgCRampDisableSa
FastPkgCRampDisableFivr
SlowSlewRateForIa
SlowSlewRateForGt
SlowSlewRateForSa
SlowSlewRateForFivr

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10
Reviewed-on: https://review.coreboot.org/c/30207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lijian Zhao
2018-12-12 11:19:46 -08:00
committed by Patrick Georgi
parent 4e21dee863
commit ae75400ae3
2 changed files with 42 additions and 0 deletions
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31
src/soc/intel/cannonlake/chip.h
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@@ -263,6 +263,37 @@ struct soc_intel_cannonlake_config {
/* Intel VT configuration */
uint8_t VtdDisable;
uint8_t VmxEnable;
/*
* Acoustic Noise Mitigation
* 0b - Disable
* 1b - Enable noise mitigation
*/
uint8_t AcousticNoiseMitigation;
/*
* Disable Fast Package C-state ramping
* Need to set AcousticNoiseMitigation = '1' first
* 0b - Enabled
* 1b - Disabled
*/
uint8_t FastPkgCRampDisableIa;
uint8_t FastPkgCRampDisableGt;
uint8_t FastPkgCRampDisableSa;
uint8_t FastPkgCRampDisableFivr;
/*
* Adjust the VR slew rates
* Need to set AcousticNoiseMitigation = '1' first
* 000b - Fast/2
* 001b - Fast/4
* 010b - Fast/8
* 011b - Fast/16
*/
uint8_t SlowSlewRateForIa;
uint8_t SlowSlewRateForGt;
uint8_t SlowSlewRateForSa;
uint8_t SlowSlewRateForFivr;
};
typedef struct soc_intel_cannonlake_config config_t;