ACPI: Separate ChromeOS NVS in ASL

For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.

More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.

Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -42,10 +42,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CMEM,	 32,	/* 0x30 - CBMEM TOC */
 	TOLM,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */