ACPI: Separate ChromeOS NVS in ASL

For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.

More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.

Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2021-01-12 15:23:25 +02:00
parent fa5f9b5aff
commit ae7ac8a723
14 changed files with 41 additions and 59 deletions

View File

@@ -4,23 +4,26 @@
* the mainboard's chromeos.asl
*/
VBT0, 32, // 0x000 - Boot Reason
VBT1, 32, // 0x004 - Active Main Firmware
VBT2, 32, // 0x008 - Active EC Firmware
VBT3, 16, // 0x00c - CHSW
VBT4, 2048, // 0x00e - HWID
VBT5, 512, // 0x10e - FWID
VBT6, 512, // 0x14e - FRID
VBT7, 32, // 0x18e - active main firmware type
VBT8, 32, // 0x192 - Recovery Reason
VBT9, 32, // 0x196 - FMAP base address
CHVD, 24576, // 0x19a - VDAT space filled by verified boot
VBTA, 32, // 0xd9a - pointer to smbios FWID
MEHH, 256, // 0xd9e - Management Engine Hash
RMOB, 32, // 0xdbe - RAM oops base address
RMOL, 32, // 0xdc2 - RAM oops length
ROVP, 32, // 0xdc6 - pointer to RO_VPD
ROVL, 32, // 0xdca - size of RO_VPD
RWVP, 32, // 0xdce - pointer to RW_VPD
RWVL, 32, // 0xdd2 - size of RW_VPD
Field (CNVS, ByteAcc, NoLock, Preserve)
{
VBT0, 32, // 0x000 - Boot Reason
VBT1, 32, // 0x004 - Active Main Firmware
VBT2, 32, // 0x008 - Active EC Firmware
VBT3, 16, // 0x00c - CHSW
VBT4, 2048, // 0x00e - HWID
VBT5, 512, // 0x10e - FWID
VBT6, 512, // 0x14e - FRID
VBT7, 32, // 0x18e - active main firmware type
VBT8, 32, // 0x192 - Recovery Reason
VBT9, 32, // 0x196 - FMAP base address
CHVD, 24576, // 0x19a - VDAT space filled by verified boot
VBTA, 32, // 0xd9a - pointer to smbios FWID
MEHH, 256, // 0xd9e - Management Engine Hash
RMOB, 32, // 0xdbe - RAM oops base address
RMOL, 32, // 0xdc2 - RAM oops length
ROVP, 32, // 0xdc6 - pointer to RO_VPD
ROVL, 32, // 0xdca - size of RO_VPD
RWVP, 32, // 0xdce - pointer to RW_VPD
RWVL, 32, // 0xdd2 - size of RW_VPD
// 0xdd6
}