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Intel model_106cx: change CAR to model_6ex

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Diff between model_106cx and model_6ex CAR codes suggests currently
used model_106cx CAR is not optimal - destination RAM and source ROM
of ramstage copy_and_run are only partly set cacheable.

It appears variable MTRR setting for XIP cache is left enabled on
model_106cx code, where it should have extended to cover all of Flash.

Introduces untested functional change on boards:
  intel/d945gclf
  iwave/iWRainbowG6

Deletes file:
  model_106cx/cache_as_ram.inc

Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/642
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
This commit is contained in:
Kyösti Mälkki
2012-06-28 21:50:43 +03:00
committed by Sven Schnelle
parent 4dcc5737cd
commit ae7d6ef8b7
2 changed files with 1 additions and 247 deletions
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2
src/cpu/intel/model_106cx/Makefile.inc
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@@ -1,4 +1,4 @@
driver-y += model_106cx_init.c
subdirs-y += ../../x86/name
cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc