From ae90fc0bb6c01bf21acbdc0b1b2b6bf3ea4cbc70 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 4 Apr 2023 10:04:07 +0200
Subject: [PATCH] soc/intel/xeon_sp/spr: Default to X2APIC support

When more than 255 CPU cores are present on a board
the X2APIC must be used.

Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.

Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/spr/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 7aa1fec53e..832aab5909 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -8,6 +8,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SAVE_MRC_AFTER_FSPS
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select DISABLE_ACPI_HIBERNATE
+	select DEFAULT_X2APIC_RUNTIME
 
 config CHIPSET_DEVICETREE
 	string