Add VIA CX700 support, plus VIA vt8454c reference board support.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Stefan Reinauer
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -29,6 +30,7 @@
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#define SPD_DIMM_TYPE_uDIMM (1<<3)
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#define SPD_DIMM_TYPE_mRDIMM (1<<4)
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#define SPD_DIMM_TYPE_mUDIMM (1<<5)
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#define SPD_MOD_ATTRIB 21
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#define SPD_MOD_ATTRIB_DIFCK 0x20
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#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
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@ -39,6 +41,15 @@
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#define SPD_DIMM_CONF_TYPE_ECC 0x02
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#define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */
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#define SPD_CAS_LAT_MIN_X_1 23
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#define SPD_CAS_LAT_MAX_X_1 24
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#define SPD_CAS_LAT_MIN_X_2 25
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#define SPD_CAS_LAT_MAX_X_2 26
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#define SPD_BURST_LENGTHS 16
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#define SPD_BURST_LENGTHS_4 (1<<2)
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#define SPD_BURST_LENGTHS_8 (1<<3)
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#define SPD_ROW_NUM 3 /* Number of Row addresses */
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#define SPD_COL_NUM 4 /* Number of Column addresses */
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#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on
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@ -82,6 +93,7 @@
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#define SPD_TWTR 37 /* x */
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#define SPD_TRTP 38 /* x */
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#define SPD_EX_TRC_TRFC 40
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#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
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#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
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