soc/intel/common: Enable support to write protect SPI flash range

Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.

BUG=chrome-os-partner:58896

Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/common/Kconfig

@@ -9,6 +9,10 @@ config CACHE_MRC_SETTINGS
 	bool "Save cached MRC settings"
 	default n
 
+config SOC_INTEL_COMMON_SPI_PROTECT
+	bool
+	default n
+
 if CACHE_MRC_SETTINGS
 
 config MRC_SETTINGS_CACHE_BASE