sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/*/*: use ACPIMMIO common block wherever possible

Browse Source 
TEST=boot PC Engines apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Michał Żygowski
2019-12-01 17:42:04 +01:00
committed by Kyösti Mälkki
parent cbbfb702f6
commit af258cc179
37 changed files with 663 additions and 746 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/amd/bettong/boardid.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/mmio.h>
#include <southbridge/amd/common/amd_defs.h>
#include <boardid.h>
@@ -30,17 +31,15 @@
*/
uint32_t board_id(void)
{
void *gpiommioaddr;
u8 value = 0;
u8 boardrev = 0;
char boardid;
gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500;
value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */
value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */
boardrev = value & 1;
value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */
value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */
boardrev |= (value & 1) << 1;
value = read8(gpiommioaddr + (5 << 2) + 2); /* agpio5: board_id0 */
value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */
boardrev |= (value & 1) << 2;
boardid = 'A' + boardrev;

8
src/mainboard/amd/db-ft3b-lc/romstage.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -34,8 +35,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
pm_io_write8(0xd2, 0);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
@@ -47,7 +47,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb)
{
/* After AMD_INIT_ENV -> move to ramstage ? */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
pm_io_write8(0xea, 1);
}

180
src/mainboard/amd/inagua/BiosCallOuts.c
View File

@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -46,76 +47,68 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
case VOLT1_35:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
return Status;
}
@@ -130,70 +123,67 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId)
{
case 4:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
}
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
case 4:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
}
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
}
}
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
return Status;
}

12
src/mainboard/amd/inagua/mainboard.c
View File

@@ -16,7 +16,6 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */
static void init_gpios(void)
{
@@ -34,16 +33,15 @@ static void init_gpios(void)
/* Multi-function pins switch to GPIO0-35, these pins are shared with
* PCI pins, make sure Hudson PCI device is disabled.
*/
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
/* select IOMux to function1/2, corresponds to GPIO */
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
/* output low */
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
gpio_100_write8(0x20, 0x48);
gpio_100_write8(0x32, 0x48);
}

22
src/mainboard/amd/lamar/romstage.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -28,25 +29,8 @@
static void romstage_main_template(void)
{
u32 val;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
* replicated in every reference design since Parmer, so it is
* believed to be required even though it is not documented in
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
hudson_lpc_decode();
outb(0x24, 0xCD6);
outb(0x01, 0xCD7);
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */
misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */
if (!cpu_init_detectedx) {
post_code(0x30);

7
src/mainboard/amd/olivehill/romstage.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -30,12 +31,10 @@ void board_BeforeAgesa(struct sysinfo *cb)
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
pm_io_write8(0xd2, 0);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
pm_io_write8(0xea, 1);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);

7
src/mainboard/amd/olivehillplus/romstage.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -34,8 +35,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
pm_io_write8(0xd2, 0);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
@@ -64,6 +64,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb)
{
/* After AMD_INIT_ENV -> move to ramstage ? */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
pm_io_write8(0xea, 1);
}

7
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <stdlib.h>
@@ -60,11 +61,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;

11
src/mainboard/amd/persimmon/mainboard.c
View File

@@ -126,12 +126,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
write8(misc_mem_clk_cntrl + 0, 0xFF);
write8(misc_mem_clk_cntrl + 1, 0x00);
write8(misc_mem_clk_cntrl + 2, 0x00);
write8(misc_mem_clk_cntrl + 3, 0x00);
write8(misc_mem_clk_cntrl + 4, 0x00);
misc_write8(0, 0xff);
misc_write8(1, 0);
misc_write8(2, 0);
misc_write8(3, 0);
misc_write8(4, 0);
/*
* Initialize ASF registers to an arbitrary address because someone

280
src/mainboard/amd/south_station/BiosCallOuts.c
View File

@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -37,166 +38,151 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
UINT8 TempData8;
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Status = AGESA_SUCCESS;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
switch(MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
return Status;
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId)
{
case 4:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
FcnData = Data;
ResetInfo = ConfigPtr;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
case 4:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
}

20
src/mainboard/amd/south_station/mainboard.c
View File

@@ -17,7 +17,6 @@
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */
/**
* Southstation using SB GPIO 17/18 to control the Red/Green LED
@@ -25,26 +24,21 @@
*/
static void southstation_led_init(void)
{
#define GPIO_FUNCTION 2 //GPIO function
#define SB_GPIO_REG17 17 //Red Light
#define SB_GPIO_REG18 18 //Green Light
/* multi-function pins switch to GPIO0-35 */
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
/* select IOMux to function2, corresponds to GPIO */
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
iomux_write8(0x11, (iomux_read8(0x11) & 0xfc) | 2);
iomux_write8(0x12, (iomux_read8(0x12) & 0xfc) | 2);
/* Lighting test */
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
gpio_100_write8(0x11, 0x08); //output high
gpio_100_write8(0x12, 0x08);
mdelay(100);
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
gpio_100_write8(0x11, 0x48); //output low
gpio_100_write8(0x12, 0x48);
}
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/

7
src/mainboard/amd/thatcher/romstage.c
View File

@@ -14,6 +14,7 @@
*/
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <console/console.h>
@@ -47,9 +48,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
post_code(0x31);
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
pm_io_write8(0x24, 1);
pm_io_write8(0xea, 1);
gpio_100_write8(0x1, 0x98);
}

280
src/mainboard/amd/union_station/BiosCallOuts.c
View File

@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -37,166 +38,151 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
UINT8 TempData8;
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Status = AGESA_SUCCESS;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
switch(MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
return Status;
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId)
{
case 4:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl)
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
FcnData = Data;
ResetInfo = ConfigPtr;
AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
case 4:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6;
/* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6;
/* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6;
/* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
}