mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Kyösti Mälkki
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cbbfb702f6
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@@ -59,32 +59,41 @@ static const u16 sio_init_table[] = { // hi = offset, lo = value
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static void init(struct device *dev)
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{
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volatile u8 *spi_base; // base addr of Hudson's SPI host controller
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volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */
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int i;
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printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
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/* Init Hudson GPIOs. */
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printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
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FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
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FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
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FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
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FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
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FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
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FCH_IOMUX(57) = 1;
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FCH_GPIO (57) = 0x28;
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FCH_IOMUX(58) = 1;
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FCH_GPIO (58) = 0x28;
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FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
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FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
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FCH_IOMUX(61) = 2; // default to inputs with int. PU
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FCH_IOMUX(62) = 2;
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FCH_IOMUX(187) = 2;
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FCH_IOMUX(188) = 2;
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FCH_IOMUX(189) = 1;
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FCH_IOMUX(190) = 1;
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FCH_IOMUX(191) = 1;
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FCH_IOMUX(192) = 1;
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if (!fch_gpio_state(197)) // just in case anyone cares
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/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
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iomux_write8(50, 2);
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/* output set to 1 as it's never needed */
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iomux_write8(50, 0xc0);
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/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
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iomux_write8(197, 2);
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/* GPIO58-56: REV_ID2-0 */
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iomux_write8(56, 1);
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/* inputs, disable int. pull-ups */
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gpio_100_write8(56, 0x28);
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iomux_write8(57, 1);
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gpio_100_write8(57, 0x28);
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iomux_write8(58, 1);
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gpio_100_write8(58, 0x28);
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/* "Gpio96": GEVENT0# signal on X2 connector (int. PU) */
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iomux_write8(96, 1);
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/* GPIO52,61,62,187-192 free to use on X2 connector */
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iomux_write8(52, 1);
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/* default to inputs with int. PU */
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iomux_write8(61, 2);
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iomux_write8(62, 2);
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iomux_write8(187, 2);
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iomux_write8(188, 2);
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iomux_write8(189, 1);
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iomux_write8(190, 1);
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iomux_write8(191, 1);
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iomux_write8(192, 1);
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/* just in case anyone cares */
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if (!fch_gpio_state(197))
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printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
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printk(BIOS_INFO, "Board revision ID: %u\n",
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fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
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@@ -99,9 +108,11 @@ static void init(struct device *dev)
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/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
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spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
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0xA0) & 0xFFFFFFE0);
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spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
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/* NormSpeed in SPI_Cntrl1 register */
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spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
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/* Notify the SMC we're alive and kicking, or after a while it will
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/*
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* Notify the SMC we're alive and kicking, or after a while it will
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* effect a power cycle and switch to the alternate BIOS chip.
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* Should be done as late as possible.
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* Failure here does not matter if watchdog was already disabled,
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@@ -122,12 +133,11 @@ static void mainboard_enable(struct device *dev)
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/* enable GPP CLK0 */
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/* disable GPP CLK1 thru SLT_GFX_CLK */
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u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
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write8(misc_mem_clk_cntrl + 0, 0x0F);
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write8(misc_mem_clk_cntrl + 1, 0x00);
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write8(misc_mem_clk_cntrl + 2, 0x00);
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write8(misc_mem_clk_cntrl + 3, 0x00);
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write8(misc_mem_clk_cntrl + 4, 0x00);
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misc_write8(0, 0x0f);
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misc_write8(1, 0);
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misc_write8(2, 0);
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misc_write8(3, 0);
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misc_write8(4, 0);
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/*
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* Initialize ASF registers to an arbitrary address because someone
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