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mb/*/*: use ACPIMMIO common block wherever possible

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TEST=boot PC Engines apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Michał Żygowski 2019-12-01 17:42:04 +01:00 committed by Kyösti Mälkki
parent cbbfb702f6
commit af258cc179
37 changed files with 663 additions and 746 deletions
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9
src/mainboard/amd/bettong/boardid.c
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@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <boardid.h> #include <boardid.h>
@ -30,17 +31,15 @@
*/ */
uint32_t board_id(void) uint32_t board_id(void)
{ {
void *gpiommioaddr;
u8 value = 0; u8 value = 0;
u8 boardrev = 0; u8 boardrev = 0;
char boardid; char boardid;
gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500; value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */
value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */
boardrev = value & 1; boardrev = value & 1;
value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */ value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */
boardrev |= (value & 1) << 1; boardrev |= (value & 1) << 1;
value = read8(gpiommioaddr + (5 << 2) + 2); /* agpio5: board_id0 */ value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */
boardrev |= (value & 1) << 2; boardrev |= (value & 1) << 2;
boardid = 'A' + boardrev; boardid = 'A' + boardrev;

8
src/mainboard/amd/db-ft3b-lc/romstage.c
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@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -34,8 +35,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial * the SoC BKDGs. Without this setting, there is no serial
* output. * output.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
@ -47,7 +47,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb) void agesa_postcar(struct sysinfo *cb)
{ {
/* After AMD_INIT_ENV -> move to ramstage ? */ pm_io_write8(0xea, 1);
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
} }

44
src/mainboard/amd/inagua/BiosCallOuts.c
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@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@ -46,21 +47,13 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
UINT8 TempData8; UINT8 TempData8;
FcnData = Data; FcnData = Data;
MemData = ConfigPtr; MemData = ConfigPtr;
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
@ -130,34 +123,27 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr) AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId) Status = AGESA_UNSUPPORTED;
{ switch (ResetInfo->ResetId) {
case 4: case 4:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
@ -167,13 +153,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
@ -183,13 +171,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }

12
src/mainboard/amd/inagua/mainboard.c
View File

@ -16,7 +16,6 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */
static void init_gpios(void) static void init_gpios(void)
{ {
@ -34,16 +33,15 @@ static void init_gpios(void)
/* Multi-function pins switch to GPIO0-35, these pins are shared with /* Multi-function pins switch to GPIO0-35, these pins are shared with
* PCI pins, make sure Hudson PCI device is disabled. * PCI pins, make sure Hudson PCI device is disabled.
*/ */
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
/* select IOMux to function1/2, corresponds to GPIO */ /* select IOMux to function1/2, corresponds to GPIO */
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1); iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2); iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
/* output low */ /* output low */
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48); gpio_100_write8(0x20, 0x48);
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48); gpio_100_write8(0x32, 0x48);
} }

22
src/mainboard/amd/lamar/romstage.c
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@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -28,25 +29,8 @@
static void romstage_main_template(void) static void romstage_main_template(void)
{ {
u32 val; misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */
misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
* replicated in every reference design since Parmer, so it is
* believed to be required even though it is not documented in
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
hudson_lpc_decode();
outb(0x24, 0xCD6);
outb(0x01, 0xCD7);
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
if (!cpu_init_detectedx) { if (!cpu_init_detectedx) {
post_code(0x30); post_code(0x30);

7
src/mainboard/amd/olivehill/romstage.c
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@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -30,12 +31,10 @@ void board_BeforeAgesa(struct sysinfo *cb)
* even though the register is not documented in the Kabini BKDG. * even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code. * Otherwise the serial output is bad code.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
outb(0xea, 0xcd6); pm_io_write8(0xea, 1);
outb(0x1, 0xcd7);
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);

7
src/mainboard/amd/olivehillplus/romstage.c
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@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -34,8 +35,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial * the SoC BKDGs. Without this setting, there is no serial
* output. * output.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
@ -64,6 +64,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb) void agesa_postcar(struct sysinfo *cb)
{ {
/* After AMD_INIT_ENV -> move to ramstage ? */ /* After AMD_INIT_ENV -> move to ramstage ? */
outb(0xEA, 0xCD6); pm_io_write8(0xea, 1);
outb(0x1, 0xcd7);
} }

7
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
#include <stdlib.h> #include <stdlib.h>
@ -60,11 +61,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); Data8 = pm_io_read8(0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); Data8 = pm_io_read8(0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;

11
src/mainboard/amd/persimmon/mainboard.c
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@ -126,12 +126,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */ /* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */ /* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0xff);
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(1, 0);
write8(misc_mem_clk_cntrl + 1, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

54
src/mainboard/amd/south_station/BiosCallOuts.c
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@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@ -46,21 +47,13 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
UINT8 TempData8; UINT8 TempData8;
FcnData = Data; FcnData = Data;
MemData = ConfigPtr; MemData = ConfigPtr;
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
@ -126,73 +119,66 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
AGESA_STATUS Status; AGESA_STATUS Status;
UINTN FcnData; UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr) AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId) Status = AGESA_UNSUPPORTED;
{ switch (ResetInfo->ResetId) {
case 4: case 4:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
break; break;
case 6: case 6:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
break; break;
case 7: case 7:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }

20
src/mainboard/amd/south_station/mainboard.c
View File

@ -17,7 +17,6 @@
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <device/device.h> #include <device/device.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */
/** /**
* Southstation using SB GPIO 17/18 to control the Red/Green LED * Southstation using SB GPIO 17/18 to control the Red/Green LED
@ -25,26 +24,21 @@
*/ */
static void southstation_led_init(void) static void southstation_led_init(void)
{ {
#define GPIO_FUNCTION 2 //GPIO function
#define SB_GPIO_REG17 17 //Red Light
#define SB_GPIO_REG18 18 //Green Light
/* multi-function pins switch to GPIO0-35 */ /* multi-function pins switch to GPIO0-35 */
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
/* select IOMux to function2, corresponds to GPIO */ /* select IOMux to function2, corresponds to GPIO */
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); iomux_write8(0x11, (iomux_read8(0x11) & 0xfc) | 2);
RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); iomux_write8(0x12, (iomux_read8(0x12) & 0xfc) | 2);
/* Lighting test */ /* Lighting test */
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high gpio_100_write8(0x11, 0x08); //output high
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); gpio_100_write8(0x12, 0x08);
mdelay(100); mdelay(100);
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low gpio_100_write8(0x11, 0x48); //output low
RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); gpio_100_write8(0x12, 0x48);
} }
/********************************************** /**********************************************
* Enable the dedicated functions of the board. * Enable the dedicated functions of the board.
**********************************************/ **********************************************/

7
src/mainboard/amd/thatcher/romstage.c
View File

@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
@ -47,9 +48,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
post_code(0x31); post_code(0x31);
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x24, 0xcd6); pm_io_write8(0x24, 1);
outb(0x1, 0xcd7); pm_io_write8(0xea, 1);
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
gpio_100_write8(0x1, 0x98); gpio_100_write8(0x1, 0x98);
} }

54
src/mainboard/amd/union_station/BiosCallOuts.c
View File

@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@ -46,21 +47,13 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
UINT8 TempData8; UINT8 TempData8;
FcnData = Data; FcnData = Data;
MemData = ConfigPtr; MemData = ConfigPtr;
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
@ -126,73 +119,66 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
AGESA_STATUS Status; AGESA_STATUS Status;
UINTN FcnData; UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr) AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId) Status = AGESA_UNSUPPORTED;
{ switch (ResetInfo->ResetId) {
case 4: case 4:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 /* MXM_GPIO0. GPIO21 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
break; break;
case 6: case 6:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 /* PCIE_RST#_LAN, GPIO25 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }
break; break;
case 7: case 7:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6; Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 /* MPCIE_RST0, GPIO02 */
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }

18
src/mainboard/asrock/e350m1/BiosCallOuts.c
View File

@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
@ -43,21 +44,13 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
UINT32 AcpiMmioAddr; UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr; UINT32 GpioMmioAddr;
UINT8 Data8; UINT8 Data8;
UINT16 Data16;
UINT8 TempData8; UINT8 TempData8;
FcnData = Data; FcnData = Data;
MemData = ConfigPtr; MemData = ConfigPtr;
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
/* Get SB800 MMIO Base (AcpiMmioAddr) */ AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
@ -86,8 +79,9 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
TempData8 |= Data8; TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
/* this seems to be just copy-pasted from the AMD reference boards and needs /*
* some investigation * this seems to be just copy-pasted from the AMD reference boards and
* needs some investigation
*/ */
switch (MemData->ParameterListPtr->DDR3Voltage) { switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35: case VOLT1_35:
@ -115,7 +109,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
Data8 &= ~(UINT8)BIT6; Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
} }
// disable memory clear for boot time reduction /* disable memory clear for boot time reduction */
MemData->ParameterListPtr->EnableMemClr = FALSE; MemData->ParameterListPtr->EnableMemClr = FALSE;
return Status; return Status;
} }

14
src/mainboard/asrock/e350m1/mainboard.c
View File

@ -26,19 +26,17 @@ static void mainboard_enable(struct device *dev)
{ {
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Power off unused clock pins of GPP PCIe devices */ /* Power off unused clock pins of GPP PCIe devices
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
/*
* GPP CLK0 connected to unpopulated mini PCIe slot * GPP CLK0 connected to unpopulated mini PCIe slot
* GPP CLK1 connected to ethernet chip * GPP CLK1 connected to ethernet chip
*/ */
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(0, 0xff);
/* GPP CLK2 connected to the external USB3 controller */ /* GPP CLK2 connected to the external USB3 controller */
write8(misc_mem_clk_cntrl + 1, 0x0F); misc_write8(1, 0x0f);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(3, 0);
/* SLT_GFX_CLK connected to PCIe slot */ /* SLT_GFX_CLK connected to PCIe slot */
write8(misc_mem_clk_cntrl + 4, 0xF0); misc_write8(4, 0xf0);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

10
src/mainboard/asrock/imb-a180/bootblock.c
View File

@ -21,20 +21,14 @@
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)
{ {
u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1); pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
reg32 = misc_read32(0x28); misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
reg32 = misc_read32(0x40); misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
reg32 &= 0xffffbffb;
misc_write32(0x40, reg32);
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

2
src/mainboard/asus/am1i-a/bootblock.c
View File

@ -113,7 +113,7 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)
{ {
volatile u32 i, val; u32 val, i;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1); pm_write8(0xea, 0x1);

4
src/mainboard/asus/f2a85-m/bootblock.c
View File

@ -32,9 +32,7 @@ static void sbxxx_enable_48mhzout(void)
reg32 |= 0x00100000; reg32 |= 0x00100000;
misc_write32(0x28, reg32); misc_write32(0x28, reg32);
reg32 = misc_read32(0x40); misc_write32(0x40, misc_read32(0x40) & (~0x80u));
reg32 &= ~0x80u;
misc_write32(0x40, reg32);
} }
static void superio_init_m(void) static void superio_init_m(void)

6
src/mainboard/asus/f2a85-m/romstage.c
View File

@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <amdblocks/acpimmio.h>
#include <arch/io.h> #include <arch/io.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/smbus.h> #include <southbridge/amd/agesa/hudson/smbus.h>
@ -26,10 +27,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
post_code(0x30); post_code(0x30);
/* turn on secondary smbus at b20 */ /* turn on secondary smbus at b20 */
outb(0x28, 0xcd6); pm_write8(0x28, pm_read8(0x28) | 1);
byte = inb(0xcd7);
byte |= 1;
outb(byte, 0xcd7);
/* set DDR3 voltage */ /* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;

4
src/mainboard/bap/ode_e20XX/romstage.c
View File

@ -16,6 +16,7 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/hudson.h>
@ -29,8 +30,7 @@
void board_BeforeAgesa(struct sysinfo *cb) void board_BeforeAgesa(struct sysinfo *cb)
{ {
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
outb(0xea, 0xcd6); pm_io_write(0xea, 1);
outb(0x1, 0xcd7);
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);

7
src/mainboard/bap/ode_e21XX/romstage.c
View File

@ -14,6 +14,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -38,8 +39,7 @@ static void romstage_main_template(void)
* the SoC BKDGs. Without this setting, there is no serial * the SoC BKDGs. Without this setting, there is no serial
* output. * output.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
@ -52,6 +52,5 @@ static void romstage_main_template(void)
void agesa_postcar(struct sysinfo *cb) void agesa_postcar(struct sysinfo *cb)
{ {
/* After AMD_INIT_ENV -> move to ramstage ? */ /* After AMD_INIT_ENV -> move to ramstage ? */
outb(0xEA, 0xCD6); pm_io_write8(0xea, 1);
outb(0x1, 0xcd7);
} }

6
src/mainboard/biostar/a68n_5200/romstage.c
View File

@ -16,6 +16,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -32,13 +33,11 @@
static void sbxxx_enable_48mhzout(void) static void sbxxx_enable_48mhzout(void)
{ {
/* most likely programming to 48MHz out signal */ /* most likely programming to 48MHz out signal */
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
u32 reg32; u32 reg32;
reg32 = misc_read32(0x28); reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff; reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32); misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
reg32 = misc_read32(0x40); reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb; reg32 &= 0xffffbffb;
misc_write32(0x40, reg32); misc_write32(0x40, reg32);
@ -49,8 +48,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
u8 byte; u8 byte;
/* Enable the AcpiMmio space */ /* Enable the AcpiMmio space */
outb(0x24, 0xcd6); pm_io_write8(0x24, 1);
outb(0x1, 0xcd7);
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);

10
src/mainboard/biostar/am1ml/bootblock.c
View File

@ -61,20 +61,14 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)
{ {
u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1); pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
reg32 = misc_read32(0x28); misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
reg32 = misc_read32(0x40); misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
reg32 &= 0xffffbffb;
misc_write32(0x49, reg32);
/* Configure SIO as made under vendor BIOS */ /* Configure SIO as made under vendor BIOS */
ite_evc_conf(ENVC_DEV); ite_evc_conf(ENVC_DEV);

7
src/mainboard/elmex/pcm205400/BiosCallOuts.c
View File

@ -15,6 +15,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h> #include <SB800.h>
#include <stdlib.h> #include <stdlib.h>
@ -60,11 +61,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr) // Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27); Data8 = pm_io_read8(0x27);
Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16=Data8<<8;
WriteIo8(0xCD6, 0x26); Data8 = pm_io_read8(0x26);
Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16|=Data8;
AcpiMmioAddr = (UINT32)Data16 << 16; AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;

11
src/mainboard/elmex/pcm205400/mainboard.c
View File

@ -126,12 +126,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */ /* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */ /* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0xff);
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(1, 0);
write8(misc_mem_clk_cntrl + 1, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

15
src/mainboard/gizmosphere/gizmo/mainboard.c
View File

@ -14,12 +14,12 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <amdblocks/acpimmio.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
/********************************************** /**********************************************
* Enable the dedicated functions of the board. * Enable the dedicated functions of the board.
@ -30,18 +30,17 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */ /* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */ /* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0xFF);
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(1, 0);
write8(misc_mem_clk_cntrl + 1, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Force the onboard SATA port to GEN2 speed. * Force the onboard SATA port to GEN2 speed.
* The offboard SATA port can remain at GEN3. * The offboard SATA port can remain at GEN3.
*/ */
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); pm_write8(0xda, (pm_read8(0xda) & 0xfb) | 0x04);
} }
static void mainboard_final(void *chip_info) static void mainboard_final(void *chip_info)

19
src/mainboard/gizmosphere/gizmo2/romstage.c
View File

@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <amdblocks/acpimmio.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -29,21 +30,5 @@ void board_BeforeAgesa(struct sysinfo *cb)
* even though the register is not documented in the Kabini BKDG. * even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code. * Otherwise the serial output is bad code.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
} }
#if 0
/* LPC clock? Should happen before enable_serial. */
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for(i = 0; i < 200000; i++)
val = inb(0xcd6);
#endif
#if 0
/* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
#endif

28
src/mainboard/hp/abm/romstage.c
View File

@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <amdblocks/acpimmio.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -26,7 +27,7 @@
void board_BeforeAgesa(struct sysinfo *cb) void board_BeforeAgesa(struct sysinfo *cb)
{ {
u32 reg32; u32 t32;
/* For serial port option, plug-in card on LPC. */ /* For serial port option, plug-in card on LPC. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@ -37,32 +38,21 @@ void board_BeforeAgesa(struct sysinfo *cb)
* even though the register is not documented in the Kabini BKDG. * even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code. * Otherwise the serial output is bad code.
*/ */
outb(0xD2, 0xcd6); pm_io_write8(0xd2, 0);
outb(0x00, 0xcd7);
/* Enable the AcpiMmio space */ /* Enable the AcpiMmio space */
outb(0x24, 0xcd6); pm_io_write8(0x24, 1);
outb(0x01, 0xcd7);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
reg32 = misc_read32(0x28); t32 = misc_read32(0x28);
reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
reg32 |= 0x00010000; // Set bit 16 for 25MHz t32 |= 0x00010000; // Set bit 16 for 25MHz
misc_write32(0x28, reg32); misc_write(0x28, t32);
/* Enable Auxiliary OSCOUT1/OSCOUT2 */ /* Enable Auxiliary OSCOUT1/OSCOUT2 */
reg32 = misc_read32(0x40; t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b);
reg32 &= 0xffffff7b; // clear 2, 7
misc_write32(0x40, reg32);
nct5104d_enable_uartd(SERIAL_DEV); nct5104d_enable_uartd(SERIAL_DEV);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
} }
#if 0
/* Was before copy_and_run. */
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
#endif

7
src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
View File

@ -17,6 +17,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <amdlib.h> #include <amdlib.h>
#include <amdblocks/acpimmio.h>
#include <vendorcode/amd/cimx/sb800/SB800.h> #include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
@ -63,11 +64,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data; FcnData = Data;
ResetInfo = ConfigPtr; ResetInfo = ConfigPtr;
/* Get SB800 MMIO Base (AcpiMmioAddr) */ /* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27); Data8 = pm_io_read8(0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8 << 8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); Data8 = pm_io_read8(0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8; Data16 |= Data8;
AcpiMmioAddr = (uint32_t)Data16 << 16; AcpiMmioAddr = (uint32_t)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;

11
src/mainboard/jetway/nf81-t56n-lf/mainboard.c
View File

@ -128,12 +128,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK3 (interleaved) */ /* enable GPP CLK0 thru CLK3 (interleaved) */
/* disable GPP CLK4 thru SLT_GFX_CLK */ /* disable GPP CLK4 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0xff);
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(1, 0xff);
write8(misc_mem_clk_cntrl + 1, 0xFF); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

68
src/mainboard/lippert/frontrunner-af/mainboard.c
View File

@ -59,32 +59,41 @@ static const u16 sio_init_table[] = { // hi = offset, lo = value
static void init(struct device *dev) static void init(struct device *dev)
{ {
volatile u8 *spi_base; // base addr of Hudson's SPI host controller volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */
int i; int i;
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__); printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
/* Init Hudson GPIOs. */ /* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices /* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed iomux_write8(50, 2);
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU) /* output set to 1 as it's never needed */
FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 iomux_write8(50, 0xc0);
FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups /* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
FCH_IOMUX(57) = 1; iomux_write8(197, 2);
FCH_GPIO (57) = 0x28; /* GPIO58-56: REV_ID2-0 */
FCH_IOMUX(58) = 1; iomux_write8(56, 1);
FCH_GPIO (58) = 0x28; /* inputs, disable int. pull-ups */
FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) gpio_100_write8(56, 0x28);
FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector iomux_write8(57, 1);
FCH_IOMUX(61) = 2; // default to inputs with int. PU gpio_100_write8(57, 0x28);
FCH_IOMUX(62) = 2; iomux_write8(58, 1);
FCH_IOMUX(187) = 2; gpio_100_write8(58, 0x28);
FCH_IOMUX(188) = 2; /* "Gpio96": GEVENT0# signal on X2 connector (int. PU) */
FCH_IOMUX(189) = 1; iomux_write8(96, 1);
FCH_IOMUX(190) = 1; /* GPIO52,61,62,187-192 free to use on X2 connector */
FCH_IOMUX(191) = 1; iomux_write8(52, 1);
FCH_IOMUX(192) = 1; /* default to inputs with int. PU */
if (!fch_gpio_state(197)) // just in case anyone cares iomux_write8(61, 2);
iomux_write8(62, 2);
iomux_write8(187, 2);
iomux_write8(188, 2);
iomux_write8(189, 1);
iomux_write8(190, 1);
iomux_write8(191, 1);
iomux_write8(192, 1);
/* just in case anyone cares */
if (!fch_gpio_state(197))
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
printk(BIOS_INFO, "Board revision ID: %u\n", printk(BIOS_INFO, "Board revision ID: %u\n",
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
@ -99,9 +108,11 @@ static void init(struct device *dev)
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3), spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
0xA0) & 0xFFFFFFE0); 0xA0) & 0xFFFFFFE0);
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register /* NormSpeed in SPI_Cntrl1 register */
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
/* Notify the SMC we're alive and kicking, or after a while it will /*
* Notify the SMC we're alive and kicking, or after a while it will
* effect a power cycle and switch to the alternate BIOS chip. * effect a power cycle and switch to the alternate BIOS chip.
* Should be done as late as possible. * Should be done as late as possible.
* Failure here does not matter if watchdog was already disabled, * Failure here does not matter if watchdog was already disabled,
@ -122,12 +133,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 */ /* enable GPP CLK0 */
/* disable GPP CLK1 thru SLT_GFX_CLK */ /* disable GPP CLK1 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0x0f);
write8(misc_mem_clk_cntrl + 0, 0x0F); misc_write8(1, 0);
write8(misc_mem_clk_cntrl + 1, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

85
src/mainboard/lippert/toucan-af/mainboard.c
View File

@ -27,36 +27,52 @@
static void init(struct device *dev) static void init(struct device *dev)
{ {
volatile u8 *spi_base; // base addr of Hudson's SPI host controller volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__); printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
/* Init Hudson GPIOs. */ /* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices /* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed iomux_write8(50, 2);
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# /* output set to 1 as it's never needed */
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up iomux_write8(50, 0xc0);
FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 /* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups iomux_write8(197, 2);
FCH_IOMUX(57) = 1; /* input, disable int. pull-up */
FCH_GPIO (57) = 0x28; gpio_100_write8(197, 0x28);
FCH_IOMUX(58) = 1; /* GPIO58-56: REV_ID2-0 */
FCH_GPIO (58) = 0x28; iomux_write8(56, 1);
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector /* inputs, disable int. pull-ups */
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0 gpio_100_write8(56, 0x28);
FCH_IOMUX(188) = 2; iomux_write8(57, 1);
FCH_GPIO (188) = 0x08; gpio_100_write8(57, 0x28);
FCH_IOMUX(166) = 2; iomux_write8(58, 1);
FCH_GPIO (166) = 0x08; gpio_100_write8(58, 0x28);
// needed to make GPO160 work (Hudson Register Reference section 2.3.6.1) /* GPIO187,188,166,GPO160: GPO0-3 on COM Express connector */
FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01; iomux_write8(187, 2);
FCH_IOMUX(160) = 1; /* outputs, disable PUs, default to 0 */
FCH_GPIO (160) = 0x08; gpio_100_write8(187, 0x08);
FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector iomux_write8(188, 2);
FCH_IOMUX(190) = 1; // default to inputs with int. PU gpio_100_write8(188, 0x08);
FCH_IOMUX(191) = 1; iomux_write8(166, 2);
FCH_IOMUX(192) = 1; gpio_100_write8(166, 0x08);
if (!fch_gpio_state(197)) // just in case anyone cares /*
* needed to make GPO160 work (Hudson Register Reference
* section 2.3.6.1)
*/
pm_write8(0xdc, pm_read8(0xdc) & (~0x80));
pm_write8(0xe6, (pm_read8(0xe6) & (~0x02)) | 1);
iomux_write8(160, 1);
gpio_100_write8(160, 0x08);
/* GPIO189-192: GPI0-3 on COM Express connector */
iomux_write8(189, 1);
/* default to inputs with int. PU */
iomux_write8(190, 1);
iomux_write8(191, 1);
iomux_write8(192, 1);
/* just in case anyone cares */
if (!fch_gpio_state(197))
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
printk(BIOS_INFO, "Board revision ID: %u\n", printk(BIOS_INFO, "Board revision ID: %u\n",
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
@ -64,9 +80,11 @@ static void init(struct device *dev)
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3), spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
0xA0) & 0xFFFFFFE0); 0xA0) & 0xFFFFFFE0);
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register /* NormSpeed in SPI_Cntrl1 register */
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
/* Notify the SMC we're alive and kicking, or after a while it will /*
* Notify the SMC we're alive and kicking, or after a while it will
* effect a power cycle and switch to the alternate BIOS chip. * effect a power cycle and switch to the alternate BIOS chip.
* Should be done as late as possible. * Should be done as late as possible.
* Failure here does not matter if watchdog was already disabled, * Failure here does not matter if watchdog was already disabled,
@ -87,12 +105,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK1 */ /* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */ /* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); misc_write8(0, 0xff);
write8(misc_mem_clk_cntrl + 0, 0xFF); misc_write8(1, 0);
write8(misc_mem_clk_cntrl + 1, 0x00); misc_write8(2, 0);
write8(misc_mem_clk_cntrl + 2, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(4, 0);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* /*
* Initialize ASF registers to an arbitrary address because someone * Initialize ASF registers to an arbitrary address because someone

16
src/mainboard/pcengines/apu1/gpio_ftns.c
View File

@ -27,25 +27,21 @@ uintptr_t find_gpio_base(void)
return base_addr; return base_addr;
} }
void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting) void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting)
{ {
u8 bdata; u8 bdata;
u8 *memptr;
memptr = (u8 *)(base_addr + IOMUX_OFFSET + gpio); iomux_write8(gpio, iomux_ftn);
*memptr = iomux_ftn;
memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); bdata = gpio_100_read8(gpio);
bdata = *memptr;
bdata &= 0x07; bdata &= 0x07;
bdata |= setting; /* set direction and data value */ bdata |= setting; /* set direction and data value */
*memptr = bdata; gpio_100_write8(gpio, bdata);
} }
u8 read_gpio(uintptr_t base_addr, u32 gpio) u8 read_gpio(uintptr_t base_addr, u8 gpio)
{ {
u8 *memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0;
return (*memptr & GPIO_DATA_IN) ? 1 : 0;
} }
int get_spd_offset(void) int get_spd_offset(void)

4
src/mainboard/pcengines/apu1/gpio_ftns.h
View File

@ -19,8 +19,8 @@
#include <stdint.h> #include <stdint.h>
uintptr_t find_gpio_base(void); uintptr_t find_gpio_base(void);
void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting); void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting);
u8 read_gpio(uintptr_t base_addr, u32 gpio); u8 read_gpio(uintptr_t base_addr, u8 gpio);
int get_spd_offset(void); int get_spd_offset(void);
#define IOMUX_OFFSET 0xD00 #define IOMUX_OFFSET 0xD00

19
src/mainboard/pcengines/apu1/mainboard.c
View File

@ -14,6 +14,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <amdblocks/acpimmio.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/mmio.h> #include <device/mmio.h>
@ -181,17 +182,17 @@ static void mainboard_enable(struct device *dev)
config_gpio_mux(); config_gpio_mux();
config_addon_uart(); config_addon_uart();
/* Power off unused clock pins of GPP PCIe devices */ /* Power off unused clock pins of GPP PCIe devices
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); * GPP CLK0-2 are connected to the 3 ethernet chips
/* GPP CLK0-2 are connected to the 3 ethernet chips * GPP CLK3-4 are connected to the miniPCIe slots
* GPP CLK3-4 are connected to the miniPCIe slots */ */
write8(misc_mem_clk_cntrl + 0, 0x21); misc_write8(0, 0x21);
write8(misc_mem_clk_cntrl + 1, 0x43); misc_write8(1, 0x43);
/* GPP CLK5 is only connected to test pads -> disable */ /* GPP CLK5 is only connected to test pads -> disable */
write8(misc_mem_clk_cntrl + 2, 0x05); misc_write8(2, 0x05);
/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
write8(misc_mem_clk_cntrl + 3, 0x00); misc_write8(3, 0);
write8(misc_mem_clk_cntrl + 4, 0x00); misc_write8(4, 0);
/* Initialize the PIRQ data structures for consumption */ /* Initialize the PIRQ data structures for consumption */
pirq_setup(); pirq_setup();

56
src/mainboard/pcengines/apu2/gpio_ftns.c
View File

@ -14,55 +14,75 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <FchPlatform.h> #include <FchPlatform.h>
#include "gpio_ftns.h" #include "gpio_ftns.h"
void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) static u32 gpio_read_wrapper(u32 gpio)
{
if (gpio < 0x100)
return gpio0_read32(gpio & 0xff);
else if (gpio >= 0x100 && gpio < 0x200)
return gpio1_read32(gpio & 0xff);
else if (gpio >= 0x200 && gpio < 0x300)
return gpio2_read32(gpio & 0xff);
die("Invalid GPIO");
}
static void gpio_write_wrapper(u32 gpio, u32 setting)
{
if (gpio < 0x100)
gpio0_write32(gpio & 0xff, setting);
else if (gpio >= 0x100 && gpio < 0x200)
gpio1_write32(gpio & 0xff, setting);
else if (gpio >= 0x200 && gpio < 0x300)
gpio2_write32(gpio & 0xff, setting);
}
void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
{ {
u32 bdata; u32 bdata;
bdata = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET bdata = gpio_read_wrapper(gpio);
+ gpio));
/* out the data value to prevent glitches */ /* out the data value to prevent glitches */
bdata |= (setting & GPIO_OUTPUT_ENABLE); bdata |= (setting & GPIO_OUTPUT_ENABLE);
write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata); gpio_write_wrapper(gpio, bdata);
/* set direction and data value */ /* set direction and data value */
bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE
| GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE)); | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));
write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata); gpio_write_wrapper(gpio, bdata);
write8((volatile void *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio), iomux_write8(iomux_gpio, iomux_ftn & 0x3);
iomux_ftn & 0x3);
} }
u8 read_gpio(u32 gpio) u8 read_gpio(u32 gpio)
{ {
u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET return (gpio_read_wrapper(gpio) & GPIO_PIN_STS) ? 1 : 0;
+ gpio));
return (status & GPIO_PIN_STS) ? 1 : 0;
} }
void write_gpio(u32 gpio, u8 value) void write_gpio(u32 gpio, u8 value)
{ {
u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET u32 status = gpio_read_wrapper(gpio);
+ gpio));
status &= ~GPIO_OUTPUT_VALUE; status &= ~GPIO_OUTPUT_VALUE;
status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0; status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;
write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), status); gpio_write_wrapper(gpio, status);
} }
int get_spd_offset(void) int get_spd_offset(void)
{ {
u8 index = 0; u8 index = 0;
/* One SPD file contains all 4 options, determine which index to /*
* One SPD file contains all 4 options, determine which index to
* read here, then call into the standard routines. * read here, then call into the standard routines.
*/ */
u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); if (gpio1_read8(0x02) & BIT0)
if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; index |= BIT0;
if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; if (gpio1_read8(0x06) & BIT0)
index |= BIT1;
return index; return index;
} }

2
src/mainboard/pcengines/apu2/gpio_ftns.h
View File

@ -16,7 +16,7 @@
#ifndef GPIO_FTNS_H #ifndef GPIO_FTNS_H
#define GPIO_FTNS_H #define GPIO_FTNS_H
void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
u8 read_gpio(u32 gpio); u8 read_gpio(u32 gpio);
void write_gpio(u32 gpio, u8 value); void write_gpio(u32 gpio, u8 value);
int get_spd_offset(void); int get_spd_offset(void);