soc/intel: Move pmc_clear_pmcon_sts() into IA common code

This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.

Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
   register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.

SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.

BUG=b:211954778
TEST=Able to build brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/alderlake/Kconfig

@@ -104,6 +104,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_CSE_SEND_EOP_EARLY
 	select SOC_INTEL_CSE_SET_EOP
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/alderlake/include/soc/pm.h

@@ -162,9 +162,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 #endif /* !defined(__ACPI__) */

src/soc/intel/alderlake/pmutil.c

@@ -133,20 +133,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/apollolake/Kconfig

@@ -107,6 +107,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SOC_INTEL_NO_BOOTGUARD_MSR
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/apollolake/include/soc/pm.h

@@ -242,7 +242,4 @@ uint8_t *pmc_mmio_regs(void);
 /* STM Support */
 uint16_t get_pmbase(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 #endif

src/soc/intel/apollolake/pmutil.c

@@ -237,17 +237,3 @@ void pmc_soc_set_afterg3_en(const bool on)
 		reg32 |= SLEEP_AFTER_POWER_FAIL;
 	write32p(gen_pmcon1, reg32);
 }
-
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON1);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON1), reg_val);
-}

src/soc/intel/cannonlake/Kconfig

@@ -105,6 +105,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/cannonlake/include/soc/pm.h

@@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 

src/soc/intel/cannonlake/pmutil.c

@@ -127,20 +127,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/common/block/include/intelblocks/pmclib.h

@@ -178,6 +178,9 @@ int pmc_fill_power_state(struct chipset_power_state *ps);
  */
 void pmc_gpe_init(void);
 
+/* Clear PMC GEN_PMCON_A register status bits */
+void pmc_clear_pmcon_sts(void);
+
 /* Power Management Utility Functions. */
 
 /* Returns PMC base address */

src/soc/intel/common/block/pmc/Kconfig

@@ -10,6 +10,12 @@ config SOC_INTEL_COMMON_BLOCK_PMC
 
 if SOC_INTEL_COMMON_BLOCK_PMC
 
+config SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
+	bool
+	help
+	  Select this on platforms where the PMC register for PM configuration (i.e.,
+	  GEN_PMCON_A/B etc. are memory mapped).
+
 config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	default y
 

src/soc/intel/common/block/pmc/pmc.c

@@ -7,6 +7,7 @@
 #include <device/pci_ids.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/pmc.h>
+#include <intelblocks/pmclib.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 

src/soc/intel/common/block/pmc/pmclib.c

@@ -5,6 +5,7 @@
 #include <assert.h>
 #include <bootmode.h>
 #include <device/mmio.h>
+#include <device/pci.h>
 #include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
@@ -14,6 +15,7 @@
 #include <intelblocks/tco.h>
 #include <option.h>
 #include <security/vboot/vboot_common.h>
+#include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <stdint.h>
 #include <string.h>
@@ -580,6 +582,44 @@ void pmc_gpe_init(void)
 	gpio_route_gpe(dw0, dw1, dw2);
 }
 
+#if ENV_RAMSTAGE
+static void pmc_clear_pmcon_sts_mmio(void)
+{
+	uint8_t *addr = pmc_mmio_regs();
+
+	clrbits32((addr + GEN_PMCON_A), MS4V);
+}
+
+static void pmc_clear_pmcon_sts_pci(void)
+{
+	struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
+	if (!dev)
+		return;
+
+	pci_and_config32(dev, GEN_PMCON_A, ~MS4V);
+}
+
+/*
+ * Clear PMC GEN_PMCON_A register status bits:
+ * SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+ * while retaining MS4V write-1-to-clear bit
+ */
+void pmc_clear_pmcon_sts(void)
+{
+	/*
+	 * Accessing PMC GEN_PMCON_A register differs between different Intel chipsets.
+	 * Typically, there are two possible ways to perform GEN_PMCON_A register programming
+	 * (like `pmc_clear_pmcon_sts()`) as:
+	 * 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register.
+	 * 2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
+	 */
+	if (CONFIG(SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION))
+		pmc_clear_pmcon_sts_mmio();
+	else
+		pmc_clear_pmcon_sts_pci();
+}
+#endif
+
 void pmc_set_power_failure_state(const bool target_on)
 {
 	const unsigned int state = get_uint_option("power_on_after_fail",

src/soc/intel/denverton_ns/include/soc/pm.h

@@ -48,7 +48,4 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 #endif /* _DENVERTON_NS_PM_H_ */

src/soc/intel/denverton_ns/pmutil.c

@@ -247,18 +247,3 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
 uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
 
 void clear_pmc_status(void) { /* TODO */ }
-
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	const pci_devfn_t dev = PCH_DEV_PMC;
-
-	reg_val = pci_read_config32(dev, GEN_PMCON_A);
-	/*
-	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit
-	 */
-	reg_val &= ~(MS4V);
-
-	pci_write_config32(dev, GEN_PMCON_A, reg_val);
-}

src/soc/intel/elkhartlake/Kconfig

@@ -58,6 +58,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/elkhartlake/include/soc/pm.h

@@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 #endif /* !defined(__ACPI__) */

src/soc/intel/elkhartlake/pmutil.c

@@ -126,20 +126,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/icelake/Kconfig

@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/icelake/include/soc/pm.h

@@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 

src/soc/intel/icelake/pmutil.c

@@ -126,20 +126,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/jasperlake/Kconfig

@@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_CSE_SET_EOP
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/jasperlake/include/soc/pm.h

@@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 #endif /* !defined(__ACPI__) */

src/soc/intel/jasperlake/pmutil.c

@@ -126,20 +126,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/skylake/include/soc/pm.h

@@ -189,7 +189,4 @@ static inline int deep_s5_enabled(void)
 /* STM Support */
 uint16_t get_pmbase(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 #endif

src/soc/intel/skylake/pmutil.c

@@ -265,18 +265,3 @@ void pmc_soc_set_afterg3_en(const bool on)
 		reg8 |= SLEEP_AFTER_POWER_FAIL;
 	pci_write_config8(dev, GEN_PMCON_B, reg8);
 }
-
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	const pci_devfn_t dev = PCH_DEV_PMC;
-
-	reg_val = pci_read_config32(dev, GEN_PMCON_A);
-	/*
-	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit
-	 */
-	reg_val &= ~(MS4V);
-
-	pci_write_config32(dev, GEN_PMCON_A, reg_val);
-}

src/soc/intel/tigerlake/Kconfig

@@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_CSE_SET_EOP
+	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER

src/soc/intel/tigerlake/include/soc/pm.h

@@ -162,9 +162,6 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);
 #endif /* !defined(__ACPI__) */

src/soc/intel/tigerlake/pmutil.c

@@ -132,20 +132,6 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	uint8_t *addr;
-	addr = pmc_mmio_regs();
-
-	reg_val = read32(addr + GEN_PMCON_A);
-	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit */
-	reg_val &= ~(MS4V);
-
-	write32((addr + GEN_PMCON_A), reg_val);
-}
-
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE

src/soc/intel/xeon_sp/include/soc/pm.h

@@ -121,7 +121,4 @@ uint16_t get_pmbase(void);
 
 void pmc_lock_smi(void);
 
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
 #endif

src/soc/intel/xeon_sp/pmutil.c

@@ -179,18 +179,3 @@ void pmc_soc_set_afterg3_en(const bool on)
 		reg8 |= SLEEP_AFTER_POWER_FAIL;
 	pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
 }
-
-void pmc_clear_pmcon_sts(void)
-{
-	uint32_t reg_val;
-	const pci_devfn_t dev = PCH_DEV_PMC;
-
-	reg_val = pci_read_config32(dev, GEN_PMCON_A);
-	/*
-	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
-	 * while retaining MS4V write-1-to-clear bit
-	 */
-	reg_val &= ~(MS4V);
-
-	pci_write_config32(dev, GEN_PMCON_A, reg_val);
-}