sb/intel: Use bool for PCIe coalescing option

Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.

Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/bd82x6x/chip.h

@@ -4,7 +4,7 @@
 #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
 
 #include <southbridge/intel/common/spi.h>
-#include <stdint.h>
+#include <types.h>
 
 struct southbridge_intel_bd82x6x_config {
 	/**
@@ -58,7 +58,7 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t gen4_dec;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	/* Override PCIe ASPM */
 	uint8_t pcie_aspm[8];

src/southbridge/intel/bd82x6x/pch.c

@@ -319,7 +319,7 @@ static void pch_pcie_enable(struct device *dev)
 		 * or the other devices will not be enumerated by the OS.
 		 */
 		if (!dev->enabled)
-			config->pcie_port_coalesce = 1;
+			config->pcie_port_coalesce = true;
 
 		if (config->pcie_port_coalesce)
 			printk(BIOS_INFO,

src/southbridge/intel/i82801gx/chip.h

@@ -3,7 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 
-#include <stdint.h>
+#include <types.h>
 
 enum sata_mode {
 	SATA_MODE_AHCI = 0,
@@ -61,7 +61,7 @@ struct southbridge_intel_i82801gx_config {
 	uint32_t sata_ports_implemented;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	int c4onc3_enable:1;
 	int docking_supported:1;

src/southbridge/intel/i82801gx/pcie.c

@@ -137,7 +137,7 @@ static void ich_pcie_device_set_func(int index, int pci_func)
 static void root_port_commit_config(struct device *dev)
 {
 	int i;
-	int coalesce = 0;
+	bool coalesce = false;
 
 	if (dev->chip_info != NULL) {
 		const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
@@ -145,7 +145,7 @@ static void root_port_commit_config(struct device *dev)
 	}
 
 	if (!rpc.ports[0]->enabled)
-		coalesce = 1;
+		coalesce = true;
 
 	for (i = 0; i < rpc.num_ports; i++) {
 		struct device *pcie_dev;

src/southbridge/intel/lynxpoint/chip.h

@@ -65,7 +65,7 @@ struct southbridge_intel_lynxpoint_config {
 	uint32_t gen4_dec;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	/* Force root port ASPM configuration with port bitmap */
 	uint8_t pcie_port_force_aspm;

src/southbridge/intel/lynxpoint/pcie.c

@@ -28,7 +28,7 @@ struct root_port_config {
 	u32 b0d28f0_32c;
 	u32 b0d28f4_32c;
 	u32 b0d28f5_32c;
-	int coalesce;
+	bool coalesce;
 	int gbe_port;
 	int num_ports;
 	struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -304,7 +304,7 @@ static void root_port_commit_config(void)
 
 	/* If the first root port is disabled the coalesce ports. */
 	if (!is_rp_enabled(1))
-		rpc.coalesce = 1;
+		rpc.coalesce = true;
 
 	/* Perform clock gating configuration. */
 	pcie_enable_clock_gating();