From af6a4342368343fb1bcbb68b0a921c8bc7b48ca9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 2 Mar 2021 18:30:33 +0100 Subject: [PATCH] soc/amd/cezanne/chipset.cb: rename alias for SATA controllers Renoir/Cezanne have two SATA controllers with 2 ports each, so call them sata_0 and sata_1. Signed-off-by: Felix Held Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chipset.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index e82d435afb..5e3d26982d 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -32,8 +32,8 @@ chip soc/amd/cezanne device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B - device pci 0.0 alias sata_ahci off end # SATA AHCI Mode - device pci 0.1 alias sata_raid off end # SATA Controller; SATA Raid/AHCI Mode + device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode + device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end