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mb/google/rex/var/karis: Remove SD card and ISH

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BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tyler Wang
2023-08-07 16:46:17 +08:00
committed by Matt DeVillier
parent 6bdc000112
commit af7df0fd32
3 changed files with 10 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/rex/Kconfig
View File

@@ -65,8 +65,6 @@ config BOARD_GOOGLE_MODEL_KARIS
def_bool n
select BOARD_GOOGLE_BASEBOARD_REX
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_ISH
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_SOUNDWIRE_CS42L42
select DRIVERS_SOUNDWIRE_MAX98363

24
src/mainboard/google/rex/variants/karis/gpio.c
View File

@@ -26,8 +26,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A11, 0, DEEP),
/* GPP_A12 : [] ==> EN_UCAM_PWR */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */
PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG),
/* GPP_A13 : Not connected */
PAD_NC(GPP_A13, NONE),
/* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */
PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
/* GPP_A15 : [] ==> WWAN_RST_L */
@@ -115,8 +115,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C09, NONE),
/* GPP_C10 : net NC is not present in the given design */
PAD_NC(GPP_C10, NONE),
/* GPP_C11 : [] ==> SD_CLKREQ_ODL */
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
/* GPP_C11 : Not Connected */
PAD_NC(GPP_C11, NONE),
/* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C13 : Not connected */
@@ -142,12 +142,8 @@ static const struct pad_config gpio_table[] = {
/* GPP_D00 : WCAM_MCLK_R */
PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
/* GPP_D01 : [] ==> SD_PE_WAKE_ODL */
PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG),
/* GPP_D02 : [] ==> SD_PERST_L */
PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG),
/* GPP_D03 : [] ==> EN_PP3300_SD */
PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG),
/* GPP_D01 : Not Connected */
PAD_NC(GPP_D01, NONE),
/* GPP_D04 : [] ==> EN_SPKR */
PAD_CFG_GPO(GPP_D04, 1, DEEP),
/* GPP_D05 : net NC. Test pad. */
@@ -389,8 +385,8 @@ static const struct pad_config early_gpio_table[] = {
/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_D03 : [] ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_D03, 1, DEEP),
/* GPP_D03 : Not Connected */
PAD_NC(GPP_D03, NONE),
/* GPP_E13 : [] ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
@@ -411,8 +407,8 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_C23, 0, DEEP),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
/* GPP_D02 : [] ==> SD_PERST_L */
PAD_CFG_GPO(GPP_D02, 1, DEEP),
/* GPP_D02 : Not Connected */
PAD_NC(GPP_D02, NONE),
};
const struct pad_config *variant_gpio_table(size_t *num)

30
src/mainboard/google/rex/variants/karis/overridetree.cb
View File

@@ -17,10 +17,6 @@ fw_config
option WFC_USB 0
option WFC_MIPI 1
end
field DB_SD 10 11
option SD_ABSENT 0
option SD_GL9755S 1
end
field DB_USB 12 14
option USB_UNKNOWN 0
option USB3_PS8815 1
@@ -50,10 +46,6 @@ fw_config
option VPU_DIS 0
option VPU_EN 1
end
field ISH 21
option ISH_DISABLE 0
option ISH_ENABLE 1
end
end
chip soc/intel/meteorlake
@@ -303,13 +295,6 @@ chip soc/intel/meteorlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE10 SSD card
device ref ish on
probe ISH ISH_ENABLE
chip drivers/intel/ish
register "firmware_name" = ""rex_ish.bin""
device generic 0 on end
end
end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp2 on end
device ref vpu on
@@ -736,21 +721,6 @@ chip soc/intel/meteorlake
end
end
end #PCIE6 WWAN card
device ref pcie_rp7 on
# Enable SD Card PCIE 7 using clk 2
register "pcie_rp[PCH_RP(7)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
register "srcclk_pin" = "2"
device generic 0 on end
end
probe DB_SD SD_GL9755S
end
device ref gspi0 on
probe TOUCHSCREEN TOUCHSCREEN_I2C_SPI
end