soc/intel/common/block: Move common uart function to block/uart
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
committed by
Patrick Georgi
Patrick Georgi
parent
55a8d8a772
commit
afa07f7ae4
@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation
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* Copyright (C) 2015-2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -14,106 +14,74 @@
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/uart.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <gpio.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/uart.h>
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#include <soc/bootblock.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <string.h>
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/* Serial IO UART controller legacy mode */
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#define PCR_SERIAL_IO_GPPRVRW7 0x618
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#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
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/* UART pad configuration. Support RXD and TXD for now. */
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static const struct pad_config uart_pads[][2] = {
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const struct uart_gpio_pad_config uart_gpio_pads[] = {
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{
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */
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.console_index = 0,
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.gpios = {
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
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},
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},
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{
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */
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.console_index = 1,
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.gpios = {
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
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},
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},
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{
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
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.console_index = 2,
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.gpios = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
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},
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}
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};
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#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
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uintptr_t uart_platform_base(int idx)
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const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
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void soc_uart_set_legacy_mode(void)
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{
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/* Same base address for all debug port usage. In reality UART2
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* is currently only supported. */
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return UART_BASE_0_ADDR(idx);
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}
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#endif
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void pch_uart_init(void)
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{
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uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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uart_common_init(pch_uart_get_debug_controller(), base);
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/* Put UART in byte access mode for 16550 compatibility */
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if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
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pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
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PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
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/*
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* Dummy read after setting any of GPPRVRW7.
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* Required for UART 16550 8-bit Legacy mode to become active
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*/
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lpss_clk_read(base);
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}
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gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE],
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ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE]));
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pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
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PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
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/*
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* Dummy read after setting any of GPPRVRW7.
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* Required for UART 16550 8-bit Legacy mode to become active
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*/
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lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
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}
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#if !ENV_SMM
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void pch_uart_read_resources(struct device *dev)
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struct device *soc_uart_console_to_device(int uart_console)
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{
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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/* Need to set the base and size for the resource allocator. */
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res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
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res->size = UART_DEBUG_BASE_0_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED;
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}
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}
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#endif
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bool pch_uart_init_debug_controller_on_resume(void)
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{
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global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs)
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return !!gnvs->uior;
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return false;
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}
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device_t pch_uart_get_debug_controller(void)
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{
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switch (CONFIG_UART_FOR_CONSOLE) {
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/*
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* if index is valid, this function will return corresponding structure
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* for uart console else will return NULL.
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*/
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switch (uart_console) {
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case 0:
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return PCH_DEV_UART0;
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return (struct device *)PCH_DEV_UART0;
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case 1:
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return PCH_DEV_UART1;
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return (struct device *)PCH_DEV_UART1;
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case 2:
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return (struct device *)PCH_DEV_UART2;
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default:
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return PCH_DEV_UART2;
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printk(BIOS_ERR, "Invalid UART console index\n");
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return NULL;
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}
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}
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