sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

libpayload: Add x86_64 (64-bit) support

Browse Source 
This patch introduces x86_64 (64-bit) support to the payload, building
upon the existing x86 (32-bit) architecture. Files necessary for 64-bit
compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig
option.

BUG=b:242829490
TEST=Able to verify all valid combinations between coreboot and
payload with this patch.

Payload Entry Point Behavior with below code.

+----------------+--------------------+----------------------------+
| LP_ARCH_X86_64 | Payload Entry Mode | Description                |
+----------------+--------------------+----------------------------+
| No             | 32-bit             | Direct protected mode init |
+----------------+--------------------+----------------------------+
| Yes            | 32-bit             | Protected to long mode     |
+----------------+--------------------+----------------------------+
| Yes            | 64-bit             | Long mode initialization   |
+----------------+--------------------+----------------------------+

Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-05-18 12:26:40 +00:00
parent 4244527d8c
commit afa39105d8
18 changed files with 686 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
payloads/libpayload/arch/x86/exception.c
View File

@ -34,7 +34,13 @@
#define IF_FLAG (1 << 9)
u32 exception_stack[0x400] __attribute__((aligned(8)));
#if CONFIG(LP_ARCH_X86_64)
#define REGISTER_FMT "0x%016zx"
#else
#define REGISTER_FMT "0x%08zx"
#endif
u8 exception_stack[0x400] __aligned(16);
static interrupt_handler handlers[256];
@ -143,17 +149,27 @@ static void dump_exception_state(void)
break;
}
printf("\n");
printf("EIP: 0x%08x\n", exception_state->regs.eip);
printf("REG_IP: " REGISTER_FMT "\n", exception_state->regs.reg_ip);
printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags);
printf("REG_AX: " REGISTER_FMT "\n", exception_state->regs.reg_ax);
printf("REG_BX: " REGISTER_FMT "\n", exception_state->regs.reg_bx);
printf("REG_CX: " REGISTER_FMT "\n", exception_state->regs.reg_cx);
printf("REG_DX: " REGISTER_FMT "\n", exception_state->regs.reg_dx);
printf("REG_SP: " REGISTER_FMT "\n", exception_state->regs.reg_sp);
printf("REG_BP: " REGISTER_FMT "\n", exception_state->regs.reg_bp);
printf("REG_SI: " REGISTER_FMT "\n", exception_state->regs.reg_si);
printf("REG_DI: " REGISTER_FMT "\n", exception_state->regs.reg_di);
#if CONFIG(LP_ARCH_X86_64)
printf("REG_R8: 0x%016zx\n", exception_state->regs.reg_r8);
printf("REG_R9: 0x%016zx\n", exception_state->regs.reg_r9);
printf("REG_R10: 0x%016zx\n", exception_state->regs.reg_r10);
printf("REG_R11: 0x%016zx\n", exception_state->regs.reg_r11);
printf("REG_R12: 0x%016zx\n", exception_state->regs.reg_r12);
printf("REG_R13: 0x%016zx\n", exception_state->regs.reg_r13);
printf("REG_R14: 0x%016zx\n", exception_state->regs.reg_r14);
printf("REG_R15: 0x%016zx\n", exception_state->regs.reg_r15);
#endif
printf("CS: 0x%04x\n", exception_state->regs.cs);
printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags);
printf("EAX: 0x%08x\n", exception_state->regs.eax);
printf("ECX: 0x%08x\n", exception_state->regs.ecx);
printf("EDX: 0x%08x\n", exception_state->regs.edx);
printf("EBX: 0x%08x\n", exception_state->regs.ebx);
printf("ESP: 0x%08x\n", exception_state->regs.esp);
printf("EBP: 0x%08x\n", exception_state->regs.ebp);
printf("ESI: 0x%08x\n", exception_state->regs.esi);
printf("EDI: 0x%08x\n", exception_state->regs.edi);
printf("DS: 0x%04x\n", exception_state->regs.ds);
printf("ES: 0x%04x\n", exception_state->regs.es);
printf("SS: 0x%04x\n", exception_state->regs.ss);
@ -164,7 +180,7 @@ static void dump_exception_state(void)
void exception_dispatch(void)
{
die_if(exception_state->vector >= ARRAY_SIZE(handlers),
"Invalid vector %u\n", exception_state->vector);
"Invalid vector %zu\n", exception_state->vector);
u8 vec = exception_state->vector;
@ -184,7 +200,7 @@ void exception_dispatch(void)
vec);
dump_exception_state();
dump_stack(exception_state->regs.esp, 512);
dump_stack(exception_state->regs.reg_sp, 512);
/* We don't call apic_eoi because we don't want to ack the interrupt and
allow another interrupt to wake the processor. */
halt();
@ -197,6 +213,10 @@ success:
void exception_init(void)
{
/* TODO: Add exception init code for x64, currently only supporting 32-bit code */
if (CONFIG(LP_ARCH_X86_64))
return;
exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
exception_init_asm();
}
@ -206,6 +226,17 @@ void set_interrupt_handler(u8 vector, interrupt_handler handler)
handlers[vector] = handler;
}
#if CONFIG(LP_ARCH_X86_64)
static uint64_t eflags(void)
{
uint64_t eflags;
asm volatile(
"pushfq\n\t"
"popq %0\n\t"
: "=rm" (eflags));
return eflags;
}
#else
static uint32_t eflags(void)
{
uint32_t eflags;
@ -215,6 +246,7 @@ static uint32_t eflags(void)
: "=rm" (eflags));
return eflags;
}
#endif
void enable_interrupts(void)
{