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vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode comment

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When set to 1, the link_compliance_mode element of the DXIO port
descriptor will cause the corresponding PCIe port to not be trained but
to output a compliance testing pattern instead. Update the comment to
point out that this is only a testing mode.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2023-07-13 01:21:16 +02:00
committed by Eric Lai
parent 2f7c7e8a77
commit afcd48a2f1
1 changed files with 1 additions and 1 deletions
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src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
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@@ -192,7 +192,7 @@ typedef struct __packed {
uint8_t slot_power_limit; // PCIe slot power limit uint8_t slot_power_limit; // PCIe slot power limit
uint32_t slot_power_limit_scale :2; // PCIe slot power limit scale uint32_t slot_power_limit_scale :2; // PCIe slot power limit scale
uint32_t :6; uint32_t :6;
uint32_t link_compliance_mode :1; // Force port into compliance mode uint32_t link_compliance_mode :1; // Force port into compliance testing mode
uint32_t link_safe_mode :1; // Safe mode capability uint32_t link_safe_mode :1; // Safe mode capability
uint32_t sb_link :1; // Link type uint32_t sb_link :1; // Link type
uint32_t clk_pm_support :1; // Clock power management support uint32_t clk_pm_support :1; // Clock power management support