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S3 code whitespaces changes.

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some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.

Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
zbao
2012-03-30 15:32:07 +08:00
committed by Marc Jones
parent 01bd79ff69
commit afd141d504
4 changed files with 117 additions and 117 deletions
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40
src/cpu/amd/agesa/family14/model_14_init.c
View File

@ -37,22 +37,22 @@
msr_t rdmsr_amd(u32 index) msr_t rdmsr_amd(u32 index)
{ {
msr_t result; msr_t result;
__asm__ __volatile__( __asm__ __volatile__(
"rdmsr" "rdmsr"
:"=a"(result.lo), "=d"(result.hi) :"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a) :"c"(index), "D"(0x9c5a203a)
); );
return result; return result;
} }
void wrmsr_amd(u32 index, msr_t msr) void wrmsr_amd(u32 index, msr_t msr)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"wrmsr" "wrmsr"
: /* No outputs */ : /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
); );
} }
static void model_14_init(device_t dev) static void model_14_init(device_t dev)
@ -123,18 +123,18 @@ static void model_14_init(device_t dev)
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {
.init = model_14_init, .init = model_14_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */
{ X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */
{ X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */
{ X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */
{ 0, 0 }, { 0, 0 },
}; };
static const struct cpu_driver model_14 __cpu_driver = { static const struct cpu_driver model_14 __cpu_driver = {
.ops = &cpu_dev_ops, .ops = &cpu_dev_ops,
.id_table = cpu_table, .id_table = cpu_table,
}; };

79
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS CalloutStatus; AGESA_STATUS CalloutStatus;
UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
/*
* printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func);
*/
CalloutStatus = AGESA_UNSUPPORTED; CalloutStatus = AGESA_UNSUPPORTED;
for (i = 0; i < CallOutCount; i++) { for (i = 0; i < CallOutCount; i++) {
@ -95,20 +99,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
UINT32 AvailableHeapSize; UINT32 AvailableHeapSize;
UINT8 *BiosHeapBaseAddr; UINT8 *BiosHeapBaseAddr;
UINT32 CurrNodeOffset; UINT32 CurrNodeOffset;
UINT32 PrevNodeOffset; UINT32 PrevNodeOffset;
UINT32 FreedNodeOffset; UINT32 FreedNodeOffset;
UINT32 BestFitNodeOffset; UINT32 BestFitNodeOffset;
UINT32 BestFitPrevNodeOffset; UINT32 BestFitPrevNodeOffset;
UINT32 NextFreeOffset; UINT32 NextFreeOffset;
BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *CurrNodePtr;
BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *FreedNodePtr;
BIOS_BUFFER_NODE *BestFitNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr;
BIOS_BUFFER_NODE *BestFitPrevNodePtr; BIOS_BUFFER_NODE *BestFitPrevNodePtr;
BIOS_BUFFER_NODE *NextFreePtr; BIOS_BUFFER_NODE *NextFreePtr;
BIOS_HEAP_MANAGER *BiosHeapBasePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams; AGESA_BUFFER_PARAMS *AllocParams;
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
@ -149,8 +153,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
CurrNodeOffset = CurrNodePtr->NextNodeOffset; CurrNodeOffset = CurrNodePtr->NextNodeOffset;
/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
to the end of the allocated nodes list. to the end of the allocated nodes list.
*/ */
} }
/* Find the node that best fits the requested buffer size */ /* Find the node that best fits the requested buffer size */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@ -199,7 +204,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
/* If BestFitNode is the first buffer in the list, then update /* If BestFitNode is the first buffer in the list, then update
StartOfFreedNodes to reflect the new free node StartOfFreedNodes to reflect the new free node
*/ */
if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
@ -249,7 +254,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
PrevNodeOffset = AllocNodeOffset; PrevNodeOffset = AllocNodeOffset;
while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
if (AllocNodePtr->NextNodeOffset == 0) { if (AllocNodePtr->NextNodeOffset == 0) {
return AGESA_BOUNDS_CHK; return AGESA_BOUNDS_CHK;
} }
@ -283,10 +288,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* Clear the BufferSize and NextNodeOffset of the previous first node */ /* Clear the BufferSize and NextNodeOffset of the previous first node */
FreedNodePtr->BufferSize = 0; FreedNodePtr->BufferSize = 0;
FreedNodePtr->NextNodeOffset = 0; FreedNodePtr->NextNodeOffset = 0;
} else { } else {
/* Otherwise, add freed node to the start of the list /* Otherwise, add freed node to the start of the list
Update NextNodeOffset and BufferSize to include the Update NextNodeOffset and BufferSize to include the
size of BIOS_BUFFER_NODE size of BIOS_BUFFER_NODE
*/ */
AllocNodePtr->NextNodeOffset = FreedNodeOffset; AllocNodePtr->NextNodeOffset = FreedNodeOffset;
} }
@ -294,21 +300,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
} else { } else {
/* Traverse list of freed nodes to find where the deallocated node /* Traverse list of freed nodes to find where the deallocated node
should be place should be place
*/ */
NextNodeOffset = FreedNodeOffset; NextNodeOffset = FreedNodeOffset;
NextNodePtr = FreedNodePtr; NextNodePtr = FreedNodePtr;
while (AllocNodeOffset > NextNodeOffset) { while (AllocNodeOffset > NextNodeOffset) {
PrevNodeOffset = NextNodeOffset; PrevNodeOffset = NextNodeOffset;
if (NextNodePtr->NextNodeOffset == 0) { if (NextNodePtr->NextNodeOffset == 0) {
break; break;
} }
NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodeOffset = NextNodePtr->NextNodeOffset;
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
} }
/* If deallocated node is adjacent to the next node, /* If deallocated node is adjacent to the next node,
concatenate both nodes concatenate both nodes
*/ */
if (NextNodeOffset == EndNodeOffset) { if (NextNodeOffset == EndNodeOffset) {
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
@ -322,13 +328,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr->NextNodeOffset = NextNodeOffset; AllocNodePtr->NextNodeOffset = NextNodeOffset;
} }
/* If deallocated node is adjacent to the previous node, /* If deallocated node is adjacent to the previous node,
concatenate both nodes concatenate both nodes
*/ */
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
if (AllocNodeOffset == EndNodeOffset) { if (AllocNodeOffset == EndNodeOffset) {
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
AllocNodePtr->BufferSize = 0; AllocNodePtr->BufferSize = 0;
AllocNodePtr->NextNodeOffset = 0; AllocNodePtr->NextNodeOffset = 0;
} else { } else {
@ -398,17 +405,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
// 0xCF9 (Reset Port). // 0xCF9 (Reset Port).
// //
switch (ResetType) { switch (ResetType) {
case WARM_RESET_WHENEVER: case WARM_RESET_WHENEVER:
case COLD_RESET_WHENEVER: case COLD_RESET_WHENEVER:
break; break;
case WARM_RESET_IMMEDIATELY: case WARM_RESET_IMMEDIATELY:
case COLD_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY:
Value = 0x06; Value = 0x06;
LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
break; break;
default: default:
break; break;
} }
@ -555,13 +562,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
case 4: case 4:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
@ -571,13 +578,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break; break;
case 6: case 6:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
@ -587,13 +594,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break; break;
case 7: case 7:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02

7
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
View File

@ -73,13 +73,6 @@
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------
*/ */
VOID
ExecuteFinalHltInstruction (
IN UINT32 SharedCore,
IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID VOID
SetIdtr ( SetIdtr (
IN IDT_BASE_LIMIT *IdtInfo, IN IDT_BASE_LIMIT *IdtInfo,