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S3 code whitespaces changes.

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some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.

Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
zbao
2012-03-30 15:32:07 +08:00
committed by Marc Jones
parent 01bd79ff69
commit afd141d504
4 changed files with 117 additions and 117 deletions
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40
src/cpu/amd/agesa/family14/model_14_init.c
View File

@ -37,22 +37,22 @@
msr_t rdmsr_amd(u32 index) msr_t rdmsr_amd(u32 index)
{ {
msr_t result; msr_t result;
__asm__ __volatile__( __asm__ __volatile__(
"rdmsr" "rdmsr"
:"=a"(result.lo), "=d"(result.hi) :"=a"(result.lo), "=d"(result.hi)
:"c"(index), "D"(0x9c5a203a) :"c"(index), "D"(0x9c5a203a)
); );
return result; return result;
} }
void wrmsr_amd(u32 index, msr_t msr) void wrmsr_amd(u32 index, msr_t msr)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"wrmsr" "wrmsr"
: /* No outputs */ : /* No outputs */
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
); );
} }
static void model_14_init(device_t dev) static void model_14_init(device_t dev)
@ -123,18 +123,18 @@ static void model_14_init(device_t dev)
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {
.init = model_14_init, .init = model_14_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */
{ X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */
{ X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */
{ X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */
{ 0, 0 }, { 0, 0 },
}; };
static const struct cpu_driver model_14 __cpu_driver = { static const struct cpu_driver model_14 __cpu_driver = {
.ops = &cpu_dev_ops, .ops = &cpu_dev_ops,
.id_table = cpu_table, .id_table = cpu_table,
}; };

79
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS CalloutStatus; AGESA_STATUS CalloutStatus;
UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
/*
* printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func);
*/
CalloutStatus = AGESA_UNSUPPORTED; CalloutStatus = AGESA_UNSUPPORTED;
for (i = 0; i < CallOutCount; i++) { for (i = 0; i < CallOutCount; i++) {
@ -95,20 +99,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
UINT32 AvailableHeapSize; UINT32 AvailableHeapSize;
UINT8 *BiosHeapBaseAddr; UINT8 *BiosHeapBaseAddr;
UINT32 CurrNodeOffset; UINT32 CurrNodeOffset;
UINT32 PrevNodeOffset; UINT32 PrevNodeOffset;
UINT32 FreedNodeOffset; UINT32 FreedNodeOffset;
UINT32 BestFitNodeOffset; UINT32 BestFitNodeOffset;
UINT32 BestFitPrevNodeOffset; UINT32 BestFitPrevNodeOffset;
UINT32 NextFreeOffset; UINT32 NextFreeOffset;
BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *CurrNodePtr;
BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *FreedNodePtr;
BIOS_BUFFER_NODE *BestFitNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr;
BIOS_BUFFER_NODE *BestFitPrevNodePtr; BIOS_BUFFER_NODE *BestFitPrevNodePtr;
BIOS_BUFFER_NODE *NextFreePtr; BIOS_BUFFER_NODE *NextFreePtr;
BIOS_HEAP_MANAGER *BiosHeapBasePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams; AGESA_BUFFER_PARAMS *AllocParams;
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
@ -149,8 +153,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
CurrNodeOffset = CurrNodePtr->NextNodeOffset; CurrNodeOffset = CurrNodePtr->NextNodeOffset;
/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
to the end of the allocated nodes list. to the end of the allocated nodes list.
*/ */
} }
/* Find the node that best fits the requested buffer size */ /* Find the node that best fits the requested buffer size */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@ -199,7 +204,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
/* If BestFitNode is the first buffer in the list, then update /* If BestFitNode is the first buffer in the list, then update
StartOfFreedNodes to reflect the new free node StartOfFreedNodes to reflect the new free node
*/ */
if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
@ -249,7 +254,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
PrevNodeOffset = AllocNodeOffset; PrevNodeOffset = AllocNodeOffset;
while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
if (AllocNodePtr->NextNodeOffset == 0) { if (AllocNodePtr->NextNodeOffset == 0) {
return AGESA_BOUNDS_CHK; return AGESA_BOUNDS_CHK;
} }
@ -283,10 +288,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* Clear the BufferSize and NextNodeOffset of the previous first node */ /* Clear the BufferSize and NextNodeOffset of the previous first node */
FreedNodePtr->BufferSize = 0; FreedNodePtr->BufferSize = 0;
FreedNodePtr->NextNodeOffset = 0; FreedNodePtr->NextNodeOffset = 0;
} else { } else {
/* Otherwise, add freed node to the start of the list /* Otherwise, add freed node to the start of the list
Update NextNodeOffset and BufferSize to include the Update NextNodeOffset and BufferSize to include the
size of BIOS_BUFFER_NODE size of BIOS_BUFFER_NODE
*/ */
AllocNodePtr->NextNodeOffset = FreedNodeOffset; AllocNodePtr->NextNodeOffset = FreedNodeOffset;
} }
@ -294,21 +300,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
} else { } else {
/* Traverse list of freed nodes to find where the deallocated node /* Traverse list of freed nodes to find where the deallocated node
should be place should be place
*/ */
NextNodeOffset = FreedNodeOffset; NextNodeOffset = FreedNodeOffset;
NextNodePtr = FreedNodePtr; NextNodePtr = FreedNodePtr;
while (AllocNodeOffset > NextNodeOffset) { while (AllocNodeOffset > NextNodeOffset) {
PrevNodeOffset = NextNodeOffset; PrevNodeOffset = NextNodeOffset;
if (NextNodePtr->NextNodeOffset == 0) { if (NextNodePtr->NextNodeOffset == 0) {
break; break;
} }
NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodeOffset = NextNodePtr->NextNodeOffset;
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
} }
/* If deallocated node is adjacent to the next node, /* If deallocated node is adjacent to the next node,
concatenate both nodes concatenate both nodes
*/ */
if (NextNodeOffset == EndNodeOffset) { if (NextNodeOffset == EndNodeOffset) {
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
@ -322,13 +328,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocNodePtr->NextNodeOffset = NextNodeOffset; AllocNodePtr->NextNodeOffset = NextNodeOffset;
} }
/* If deallocated node is adjacent to the previous node, /* If deallocated node is adjacent to the previous node,
concatenate both nodes concatenate both nodes
*/ */
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
if (AllocNodeOffset == EndNodeOffset) { if (AllocNodeOffset == EndNodeOffset) {
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
AllocNodePtr->BufferSize = 0; AllocNodePtr->BufferSize = 0;
AllocNodePtr->NextNodeOffset = 0; AllocNodePtr->NextNodeOffset = 0;
} else { } else {
@ -398,17 +405,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
// 0xCF9 (Reset Port). // 0xCF9 (Reset Port).
// //
switch (ResetType) { switch (ResetType) {
case WARM_RESET_WHENEVER: case WARM_RESET_WHENEVER:
case COLD_RESET_WHENEVER: case COLD_RESET_WHENEVER:
break; break;
case WARM_RESET_IMMEDIATELY: case WARM_RESET_IMMEDIATELY:
case COLD_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY:
Value = 0x06; Value = 0x06;
LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
break; break;
default: default:
break; break;
} }
@ -555,13 +562,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
case 4: case 4:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
@ -571,13 +578,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break; break;
case 6: case 6:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
@ -587,13 +594,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
break; break;
case 7: case 7:
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02

31
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
View File

@ -25,7 +25,7 @@
* *
* Copyright (c) 2011, Advanced Micro Devices, Inc. * Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright * * Redistributions of source code must retain the above copyright
@ -33,10 +33,10 @@
* * Redistributions in binary form must reproduce the above copyright * * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the * notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution. * documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of * * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission. * from this software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -47,7 +47,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* *************************************************************************** * ***************************************************************************
* *
*/ */
@ -66,47 +66,40 @@
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------
*/ */
// typedef unsigned int uintptr_t; // typedef unsigned int uintptr_t;
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------
*/ */
VOID
ExecuteFinalHltInstruction (
IN UINT32 SharedCore,
IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID VOID
SetIdtr ( SetIdtr (
IN IDT_BASE_LIMIT *IdtInfo, IN IDT_BASE_LIMIT *IdtInfo,
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
); );
VOID VOID
GetCsSelector ( GetCsSelector (
IN UINT16 *Selector, IN UINT16 *Selector,
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
); );
VOID VOID
NmiHandler ( NmiHandler (
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
); );
VOID VOID
ExecuteHltInstruction ( ExecuteHltInstruction (
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
); );
VOID VOID
ExecuteWbinvdInstruction ( ExecuteWbinvdInstruction (
IN AMD_CONFIG_PARAMS *StdHeader IN AMD_CONFIG_PARAMS *StdHeader
); );
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------

84
src/vendorcode/amd/agesa/f14/gcccar.inc
View File

@ -1,7 +1,7 @@
/* /*
* Copyright (c) 2011, Advanced Micro Devices, Inc. * Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright * * Redistributions of source code must retain the above copyright
@ -9,10 +9,10 @@
* * Redistributions in binary form must reproduce the above copyright * * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the * notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution. * documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of * * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission. * from this software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -23,9 +23,9 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
*/ */
/****************************************************************************** /******************************************************************************
* AMD Generic Encapsulated Software Architecture * AMD Generic Encapsulated Software Architecture
* *
@ -144,28 +144,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
* CPU MACROS - PUBLIC * CPU MACROS - PUBLIC
* *
****************************************************************************/ ****************************************************************************/
.macro _WRMSR .macro _WRMSR
.byte 0x0f, 0x30 .byte 0x0f, 0x30
.endm .endm
.macro _RDMSR .macro _RDMSR
.byte 0x0F, 0x32 .byte 0x0F, 0x32
.endm .endm
.macro AMD_CPUID arg0 .macro AMD_CPUID arg0
.ifb \arg0 .ifb \arg0
mov $0x1, %eax mov $0x1, %eax
.byte 0x0F, 0x0A2 /* Execute instruction */ .byte 0x0F, 0x0A2 /* Execute instruction */
bswap %eax bswap %eax
xchg %ah, %al /* Ext model in al now */ xchg %ah, %al /* Ext model in al now */
rol $0x08, %eax /* Ext model in ah, model in al */ rol $0x08, %eax /* Ext model in ah, model in al */
and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
.else .else
mov \arg0, %eax mov \arg0, %eax
.byte 0x0F, 0x0A2 .byte 0x0F, 0x0A2
.endif .endif
.endm .endm
/**************************************************************************** /****************************************************************************
* *
* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
@ -180,12 +180,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
****************************************************************************/ ****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK .macro AMD_ENABLE_STACK_FAMILY_HOOK
AMD_ENABLE_STACK_FAMILY_HOOK_F10 AMD_ENABLE_STACK_FAMILY_HOOK_F10
AMD_ENABLE_STACK_FAMILY_HOOK_F12 AMD_ENABLE_STACK_FAMILY_HOOK_F12
AMD_ENABLE_STACK_FAMILY_HOOK_F14 AMD_ENABLE_STACK_FAMILY_HOOK_F14
AMD_ENABLE_STACK_FAMILY_HOOK_F15 AMD_ENABLE_STACK_FAMILY_HOOK_F15
.endm .endm
/**************************************************************************** /****************************************************************************
* *
* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
@ -206,7 +206,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
AMD_DISABLE_STACK_FAMILY_HOOK_F15 AMD_DISABLE_STACK_FAMILY_HOOK_F15
.endm .endm
/**************************************************************************** /****************************************************************************
* *
* GET_NODE_ID_CORE_ID Macro - Stackless * GET_NODE_ID_CORE_ID Macro - Stackless
@ -238,9 +238,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
*/ */
cmp $-1, %si # Has family (node/core) already been discovered? cmp $-1, %si # Has family (node/core) already been discovered?
jnz node_core_exit # Br if yes jnz node_core_exit # Br if yes
mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
_RDMSR _RDMSR
bt $APIC_BSC, %eax # Is this the BSC? bt $APIC_BSC, %eax # Is this the BSC?
@ -249,7 +249,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
node_core_exit: node_core_exit:
.endm .endm
/**************************************************************************** /****************************************************************************
## Family 10h MACROS ## Family 10h MACROS
##*************************************************************************** ##***************************************************************************
@ -277,7 +277,7 @@ node_core_exit:
# * MSRC001_102A[ClLinesToNbDis]=1 # * MSRC001_102A[ClLinesToNbDis]=1
# * No INVD or WBINVD, no exceptions, page faults or interrupts # * No INVD or WBINVD, no exceptions, page faults or interrupts
****************************************************************************/ ****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 .macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
LOCAL fam10_enable_stack_hook_exit LOCAL fam10_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL AMD_CPUID $CPUID_MODEL
@ -310,7 +310,7 @@ node_core_exit:
jc fam10_skipClearingBit4 jc fam10_skipClearingBit4
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR _WRMSR
fam10_skipClearingBit4: fam10_skipClearingBit4:
mov %esi, %eax # load core# mov %esi, %eax # load core#
or %al, %al # If (BSP) or %al, %al # If (BSP)
@ -333,7 +333,7 @@ fam10_skipClearingBit4:
fam10_enable_stack_hook_exit: fam10_enable_stack_hook_exit:
.endm .endm
/**************************************************************************** /****************************************************************************
* *
* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
@ -357,7 +357,7 @@ fam10_enable_stack_hook_exit:
* * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[IcDisSpecTlbWr]=0
* * MSRC001_102A[ClLinesToNbDis]=0 * * MSRC001_102A[ClLinesToNbDis]=0
*****************************************************************************/ *****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
LOCAL fam10_disable_stack_hook_exit LOCAL fam10_disable_stack_hook_exit
@ -413,7 +413,7 @@ fam10_enable_stack_hook_exit:
_WRMSR # Disable the event _WRMSR # Disable the event
fam10_disable_stack_hook_exit: fam10_disable_stack_hook_exit:
.endm .endm
/**************************************************************************** /****************************************************************************
* *
@ -575,7 +575,7 @@ node_core_f10_exit:
jc fam12_skipClearingBit4 jc fam12_skipClearingBit4
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR _WRMSR
fam12_skipClearingBit4: fam12_skipClearingBit4:
mov $DE_CFG, %ecx # MSR:C001_1029 mov $DE_CFG, %ecx # MSR:C001_1029
_RDMSR _RDMSR
@ -879,7 +879,7 @@ node_core_f14_exit:
_RDMSR _RDMSR
btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
_WRMSR _WRMSR
fam15_skipClearingBit4: fam15_skipClearingBit4:
mov $LS_CFG, %ecx # MSR:C001_1020 mov $LS_CFG, %ecx # MSR:C001_1020
_RDMSR _RDMSR
@ -959,7 +959,7 @@ fam15_enable_stack_hook_exit:
btr $DIS_HW_PF, %eax # Turn on hardware prefetches btr $DIS_HW_PF, %eax # Turn on hardware prefetches
#.endif # End workaround for erratum 498 #.endif # End workaround for erratum 498
0: 0:
_WRMSR _WRMSR
#-------------------------------------------------------------------------- #--------------------------------------------------------------------------
# Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
#-------------------------------------------------------------------------- #--------------------------------------------------------------------------
@ -1121,7 +1121,7 @@ node_core_f15_shared:
#.break .if (ch == bl) # Does 2nd match MyCore#? #.break .if (ch == bl) # Does 2nd match MyCore#?
cmp %bl, %ch cmp %bl, %ch
je 9f je 9f
jmp 2f jmp 2f
#.else # No 2nd core #.else # No 2nd core
4: 4:
#.break .if (ch == bl) # Does 1st match MyCore#? #.break .if (ch == bl) # Does 1st match MyCore#?
@ -1226,7 +1226,7 @@ node_core_f15_exit:
* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*****************************************************************************/ *****************************************************************************/
.macro AMD_ENABLE_STACK .macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors # These are local labels. Declared so linker doesn't cause 'redefined label' errors
LOCAL SetupStack LOCAL SetupStack
@ -1294,7 +1294,7 @@ SetupStack:
#.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
# Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
# Clear all variable and Fixed MTRRs for non-shared cores # Clear all variable and Fixed MTRRs for non-shared cores
jnc 0f jnc 0f
mov $AMD_MTRR_VARIABLE_BASE0, %ecx mov $AMD_MTRR_VARIABLE_BASE0, %ecx
xor %eax, %eax xor %eax, %eax
xor %edx, %edx xor %edx, %edx
@ -1330,20 +1330,20 @@ SetupStack:
_WRMSR _WRMSR
#.endif # End Is_Primary #.endif # End Is_Primary
#.endif # End Stack_ReEntry #.endif # End Stack_ReEntry
0: 0:
# Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor %eax, %eax xor %eax, %eax
xor %edx, %edx xor %edx, %edx
mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
#.while (cl != 1Ah) #.while (cl != 1Ah)
jmp 1f jmp 1f
2: 2:
_WRMSR _WRMSR
inc %cl inc %cl
#.endw #.endw
1: 1:
cmp $0x1A, %cl cmp $0x1A, %cl
jne 2b jne 2b
mov $TOP_MEM2, %ecx # MSR:C001_001D mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR _WRMSR
@ -1414,7 +1414,7 @@ SetupStack:
mov %eax, %ebp mov %eax, %ebp
#.endif #.endif
0: 0:
# Now set the MTRR. Add this to already existing settings (don't clear any MTRR) # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
mov %bh, %cl # ShiftCount = ((slot# ... mov %bh, %cl # ShiftCount = ((slot# ...
@ -1570,7 +1570,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is
* Destroyed: * Destroyed:
* eax, ecx, edx, esp * eax, ecx, edx, esp
*****************************************************************************/ *****************************************************************************/
.macro AMD_DISABLE_STACK .macro AMD_DISABLE_STACK
mov %ebx, %esp # Save return address mov %ebx, %esp # Save return address