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soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition

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coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.

This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.

Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.

Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Maulik V Vaghela
2022-05-06 10:27:50 +05:30
committed by Werner Zeh
parent 37ffdf3d5c
commit afe840957c
7 changed files with 40 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/cannonlake/gpio.c
View File

@@ -74,6 +74,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -96,6 +98,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -118,6 +122,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -140,6 +146,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -162,6 +170,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,

2
src/soc/intel/cannonlake/include/soc/gpio_defs.h
View File

@@ -234,6 +234,8 @@
#define HOSTSW_OWN_REG_0 0xb0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x120
#define GPI_GPE_STS_0 0x140
#define GPI_GPE_EN_0 0x160
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define GPI_NMI_STS_0 0x1c0