soc/braswell: Fix DSP clock

The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.

Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/braswell/chip.h

@@ -33,6 +33,11 @@
 #define MEM_DDR3	0
 #define MEM_LPDDR3	1
 
+enum lpe_clk_src {
+        LPE_CLK_SRC_XTAL,
+        LPE_CLK_SRC_PLL,
+};
+
 struct soc_intel_braswell_config {
 	uint8_t enable_xdp_tap;
 	uint8_t clkreq_enable;
@@ -41,8 +46,7 @@ struct soc_intel_braswell_config {
 	int disable_slp_x_stretch_sus_fail;
 
 	/* LPE Audio Clock configuration. */
-	int lpe_codec_clk_freq; /* 19 or 25 are valid. */
-	int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
+	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
 
 	/* Native SD Card controller - override controller capabilities. */
 	uint32_t sdcard_cap_low;