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mb/google/brya/var/taeko: add HPS as generic I2C peripheral

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BUG=b:202784200
TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage

Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I400719d762b001811f809f9549fd030dff9928d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Dan Callaghan 2021-10-28 21:26:12 +11:00 committed by Tim Wawrzynczak
parent 59a348b75a
commit b00bfd0765
1 changed files with 19 additions and 0 deletions
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19
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -35,6 +35,10 @@ fw_config
option BOOT_EMMC_DISABLED 0 option BOOT_EMMC_DISABLED 0
option BOOT_EMMC_ENABLED 1 option BOOT_EMMC_ENABLED 1
end end
field HPS 17
option HPS_ABSENT 0
option HPS_PRESENT 1
end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
register "TcssAuxOri" = "1" register "TcssAuxOri" = "1"
@ -276,6 +280,21 @@ chip soc/intel/alderlake
device i2c 10 on end device i2c 10 on end
end end
end end
device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
# The address we provide here is not significant because
# neither coreboot nor Linux have a driver for HPS,
# it's only used from userspace.
device i2c 30 on
probe HPS HPS_PRESENT
end
end
end
device ref i2c5 on device ref i2c5 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""ELAN0000"" register "hid" = ""ELAN0000""