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lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230

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Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio.
Verified with schematics.

Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8358
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Nicolas Reinecke
2015-02-01 02:53:35 +01:00
committed by Kyösti Mälkki
parent 60ef456f46
commit b0922f0183
10 changed files with 60 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/lenovo/t420s/devicetree.cb
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@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "gpi8_routing" = "2" register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
register "sata_port_map" = "0x17" register "sata_port_map" = "0x17"

19
src/mainboard/lenovo/t420s/smihandler.c
View File

@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/intel/model_206ax/model_206ax.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
/* The southbridge SMI handler checks whether gnvs has a /* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler * valid pointer before calling the trap handler
*/ */
@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_gpi(u32 gpi_sts)
{ {
if (gpi_sts & (1 << 12)) if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci(); mainboard_smi_handle_ec_sci();
} }
@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE: case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */ /* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600); ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */ /* route EC_SCI to SCI */
outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
tmp |= 0x02; tmp |= 0x02;
@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */ provide a EC query function */
ec_set_ports(0x66, 0x62); ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */ /* route EC_SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN); pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */ /* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */ /* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26); gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
gpe_rout |= (2 << 26); gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
} }
} }

2
src/mainboard/lenovo/t520/devicetree.cb
View File

@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "gpi8_routing" = "2" register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
register "sata_port_map" = "0x1f" register "sata_port_map" = "0x1f"

19
src/mainboard/lenovo/t520/smihandler.c
View File

@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/intel/model_206ax/model_206ax.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
/* The southbridge SMI handler checks whether gnvs has a /* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler * valid pointer before calling the trap handler
*/ */
@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_gpi(u32 gpi_sts)
{ {
if (gpi_sts & (1 << 12)) if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci(); mainboard_smi_handle_ec_sci();
} }
@ -124,8 +127,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE: case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */ /* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600); ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */ /* route EC_SCI to SCI */
outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
tmp |= 0x02; tmp |= 0x02;
@ -137,8 +140,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */ provide a EC query function */
ec_set_ports(0x66, 0x62); ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */ /* route EC_SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN); pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
@ -178,11 +181,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */ /* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */ /* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26); gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
gpe_rout |= (2 << 26); gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
} }
} }

2
src/mainboard/lenovo/t530/devicetree.cb
View File

@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "gpi8_routing" = "2" register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x3f"

19
src/mainboard/lenovo/t530/smihandler.c
View File

@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/intel/model_206ax/model_206ax.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
/* The southbridge SMI handler checks whether gnvs has a /* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler * valid pointer before calling the trap handler
*/ */
@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_gpi(u32 gpi_sts)
{ {
if (gpi_sts & (1 << 12)) if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci(); mainboard_smi_handle_ec_sci();
} }
@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE: case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */ /* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600); ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */ /* route EC_SCI to SCI */
outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
tmp |= 0x02; tmp |= 0x02;
@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */ provide a EC query function */
ec_set_ports(0x66, 0x62); ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */ /* route EC_SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN); pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */ /* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */ /* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26); gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
gpe_rout |= (2 << 26); gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
} }
} }

2
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "gpi8_routing" = "2" register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7" register "sata_port_map" = "0x7"

19
src/mainboard/lenovo/x220/smihandler.c
View File

@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/intel/model_206ax/model_206ax.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
/* The southbridge SMI handler checks whether gnvs has a /* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler * valid pointer before calling the trap handler
*/ */
@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_gpi(u32 gpi_sts)
{ {
if (gpi_sts & (1 << 12)) if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci(); mainboard_smi_handle_ec_sci();
} }
@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE: case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */ /* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600); ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */ /* route EC_SCI to SCI */
outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
tmp |= 0x02; tmp |= 0x02;
@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */ provide a EC query function */
ec_set_ports(0x66, 0x62); ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */ /* route EC_SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN); pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */ /* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */ /* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26); gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
gpe_rout |= (2 << 26); gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
} }
} }

2
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000" register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "gpi8_routing" = "2" register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7" register "sata_port_map" = "0x7"

19
src/mainboard/lenovo/x230/smihandler.c
View File

@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/intel/model_206ax/model_206ax.h>
#define GPE_EC_SCI 1
#define GPE_EC_WAKE 13
/* The southbridge SMI handler checks whether gnvs has a /* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler * valid pointer before calling the trap handler
*/ */
@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_gpi(u32 gpi_sts)
{ {
if (gpi_sts & (1 << 12)) if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci(); mainboard_smi_handle_ec_sci();
} }
@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE: case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */ /* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600); ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */ /* route EC_SCI to SCI */
outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
tmp |= 0x02; tmp |= 0x02;
@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */ provide a EC query function */
ec_set_ports(0x66, 0x62); ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */ /* route EC_SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN); pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03; tmp &= ~0x03;
@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */ /* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */ /* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26); gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
gpe_rout |= (2 << 26); gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
} }
} }