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vendor/mediatek: Add MT8195 dram initialization code

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This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8195.

The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Ryan Chuang
2021-05-06 23:48:18 +08:00
committed by Hung-Te Lin
parent 156210a718
commit b0b8dc374a
46 changed files with 96771 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/vendorcode/mediatek/Makefile.inc
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@@ -1 +1,2 @@
subdirs-$(CONFIG_SOC_MEDIATEK_MT8192) += mt8192
subdirs-$(CONFIG_SOC_MEDIATEK_MT8195) += mt8195

5
src/vendorcode/mediatek/mt8195/Makefile.inc Normal file
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@@ -0,0 +1,5 @@
subdirs-y += dramc
CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/dramc/include -Isrc/vendorcode/mediatek/mt8195/include

1708
src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c Normal file
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File diff suppressed because it is too large Load Diff

1060
src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c Normal file
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File diff suppressed because it is too large Load Diff

751
src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c Normal file
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@@ -0,0 +1,751 @@
#include "dramc_dv_init.h"
//====================================
//TX CA delay configuration
//------------------------------------
//Notice:
//TX config with shuffle register with all data_rate the same
//if under real IC , need to banlance the PI/Dline calibrated result
//====================================
static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
u8 TX_UI;
TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need confirm
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CKE )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_ODT )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RESET)\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_WE )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CAS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RAS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA2), P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA0 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA1 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA2 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_CKE1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA0 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA1 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA2 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA3 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA4 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA5 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA6 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA7 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA4), P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA8 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA9 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA10 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA11 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA12 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA13 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA14 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA15 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_CKE )\
| P_Fld( 0 , SHU_SELPH_CA5_DLY_ODT )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_RESET )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_WE )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_CAS )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_RAS )\
| P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), P_Fld( 1 , SHU_SELPH_CA6_DLY_BA0 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_BA1 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_BA2 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_CKE1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA0 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA1 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA2 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA3 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA4 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA5 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA6 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA7 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA8), P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA8 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA9 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA10 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA11 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA12 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA13 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA14 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA15 ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//Impdance configuration
//------------------------------------
//Notice:
//ANA result depend on calibration
//====================================
static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
U8 IPM_ODT_EN;
U8 CHKCYCLE = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking
U8 TXDLY_CMD = 8; //Need algrithm support .. RL . TODO
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
IPM_ODT_EN = (DFS(group_id)->data_rate>=2667) ? 1 : 0;
if (DFS(group_id)->data_rate>=4266)
TXDLY_CMD = 0xc;
else if (DFS(group_id)->data_rate>=3733)
TXDLY_CMD = 0xb;
else if (DFS(group_id)->data_rate>=3200)
TXDLY_CMD = 0xa;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2) , P_Fld(!IPM_ODT_EN , SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1) , P_Fld(CHKCYCLE , SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE )\
| P_Fld(8 , SHU_MISC_IMPCAL1_IMPCAL_CALICNT )\
| P_Fld(4 , SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE )\
| P_Fld(0x40 , SHU_MISC_IMPCAL1_IMPCALCNT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12) , P_Fld(IPM_ODT_EN?0x1b:0x0f , SHU_CA_CMD12_RG_RIMP_REV ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1), P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS )\
| P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS )\
| P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING6) , P_Fld(TXDLY_CMD , SHU_MISC_DRVING6_IMP_TXDLY_CMD ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//RX input delay configuration by mode choose
//------------------------------------
//Notice:
//
//====================================
static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 PERBYTE_TRACK_EN = 1;//TODO
U8 DQM_TRACK_EN = 0;//TODO --following RD DBI
U8 DQM_FLOW_DQ_SEL = 3;//TODO
U8 RX_force_upd = 0;//TODO
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
if(RX_force_upd == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) \
| P_Fld(DQM_FLOW_DQ_SEL , SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 ) \
| P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 ) \
| P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) \
| P_Fld(DQM_FLOW_DQ_SEL , SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 ) \
| P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 ) \
| P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 ));
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5) , 1, CA_CMD5_RG_RX_ARCLK_DVS_EN);
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
#if ENABLE_WDQS_MODE_2
static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT)
{
switch (p->frequency)
{
case 1866:
*u1DQOE_CNT = 6;
break;
case 1600:
case 1200:
case 800:
case 600:
*u1DQOE_CNT = 5;
break;
case 933:
*u1DQOE_CNT = 4;
break;
case 400:
*u1DQOE_CNT = 9;
break;
default:
mcSHOW_ERR_MSG(("[WDQSMode2TxDQOE_CNT] frequency err!\n"));
#if __ETT__
while (1);
#endif
}
}
#endif
//====================================
// MISC shuffle register fit
//------------------------------------
//Notice:
// MISC shuffle reigster should be fixed
//====================================
static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
U8 PICG_MODE = 1;
U8 LP5_HEFF = 0;//TODO
U8 LP5WRAPEN = 1;//Could random 1bit
U8 DQSIEN_DQSSTB_MODE=0;
U8 irank = 0;
U8 LP5_CASMODE = 1; //TODO Impact AC timing 1,2,3 three mode support 1:Low Power; 2:Low Freq; 3:High Eff;
U8 WCKDUAL = 0;
U8 NEW_RANK_MODE = 1;
U8 DUALSCHEN = 1;
U8 backup_rank = 0;
U8 DQOE_OPT = 0, DQOE_CNT = 0;
#if ENABLE_WDQS_MODE_2
DQOE_OPT = 1;
WDQSMode2TxDQOE_CNT(p, &DQOE_CNT);
#endif
backup_rank = p->rank;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id));
if(LPDDR4_EN_S)
{
DUALSCHEN = (A_D->DQ_P2S_RATIO==4) ? 0 : 1;
}
else if (LPDDR5_EN_S)
{
DUALSCHEN = (A_D->CA_P2S_RATIO==2) ? 0 : 1;
}
switch(DFS(group_id)->DQSIEN_MODE)
{
case 1: {DQSIEN_DQSSTB_MODE = 1;break;}
case 2: {DQSIEN_DQSSTB_MODE = 2;break;}
case 3: {DQSIEN_DQSSTB_MODE = 3;break;}
case 6: {DQSIEN_DQSSTB_MODE = 2;break;}
case 7: {DQSIEN_DQSSTB_MODE = 3;break;}
default: mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id));
}
switch(LP5_CASMODE)
{
case 1: {WCKDUAL=0;LP5_HEFF=0;break;}
case 2: {WCKDUAL=1;LP5_HEFF=0;break;}
case 3: {WCKDUAL=0;LP5_HEFF=1;break;}
default: mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE));
}
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( 1 , SHU_COMMON0_BL4 ) \
| P_Fld( (A_D->DQ_P2S_RATIO==8) , SHU_COMMON0_FREQDIV4 ) \
| P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_FDIV2 ) \
| P_Fld( LPDDR4_EN_S , SHU_COMMON0_BC4OTF ) \
| P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));//TODO
if(LPDDR5_EN_S == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( (A_D->DQ_P2S_RATIO==16) , SHU_COMMON0_FREQDIV8 ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , SHU_COMMON0_LP5BGEN ) \
| P_Fld( (DFS(group_id)->data_rate<=3200) , SHU_COMMON0_LP5BGOTF ) \
| P_Fld( LP5_HEFF , SHU_COMMON0_LP5WCKON ) \
| P_Fld( (DFS(group_id)->data_rate>=4800) , SHU_COMMON0_DLE256EN ) \
| P_Fld( LP5WRAPEN , SHU_COMMON0_LP5WRAPEN ) \
| P_Fld( LP5_HEFF , SHU_COMMON0_LP5HEFF_MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL) , P_Fld( WCKDUAL , SHU_WCKCTRL_WCKDUAL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));//TODO
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld( 1 , SHU_ACTIMING_CONF_TREFBWIG ) \
| P_Fld( 54 , SHU_ACTIMING_CONF_SCINTV ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DCM_CTRL0) , P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE2 ) \
| P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0) , P_Fld( 1 , SHU_CONF0_ADVPREEN ) \
| P_Fld( 63 , SHU_CONF0_DMPGTIM ) \
| P_Fld( 0 , SHU_CONF0_REFTHD ) \
| P_Fld( 1 , SHU_CONF0_PBREFEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE) , P_Fld( 2 , SHU_MATYPE_MATYPE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER) , P_Fld( DUALSCHEN , SHU_SCHEDULER_DUALSCHEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_WPRE2T ));
//TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random
//OE_EXT2UI strange rule.--TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0) , P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_TX_SET0_WDATRGO ) \
| P_Fld( (DFS(group_id)->data_rate>=3200) , SHU_TX_SET0_WPST1P5T ) \
| P_Fld( DQOE_OPT , SHU_TX_SET0_DQOE_OPT ) \
| P_Fld( DQOE_CNT , SHU_TX_SET0_DQOE_CNT ) \
| P_Fld( LPDDR5_EN_S , SHU_TX_SET0_OE_EXT2UI ) \
| P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld( 0x30 , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \
| P_Fld( 1 , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \
| P_Fld( 9 , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \
| P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STBCALEN ) \
| P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STB_SELPHCALEN ) \
| P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO
//@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_PICGLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_DQSG_MODE ) \
| P_Fld( PICG_MODE , MISC_SHU_STBCAL_DQSIEN_PICG_MODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), P_Fld( PICG_MODE , MISC_SHU_RANKCTL_RANK_RXDLY_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MISC ), P_Fld( 1 , SHU_MISC_REQQUE_MAXCNT ));
for(irank = RANK_0; irank < p->support_rank_num; irank++)
{
vSetRank(p, irank);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), P_Fld( 0 , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) \
| P_Fld( (A_D->DQ_P2S_RATIO == 4) , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_CKE_CTRL) , 0 , SHURK_CKE_CTRL_CKE_DBE_CNT );
}
vSetRank(p, backup_rank);
//RODT offset TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN ) \
| P_Fld( 0 , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE ) \
| P_Fld( (NEW_RANK_MODE)?1:PICG_MODE , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE ) \
| P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 4)?2:0) , MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET ) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 4)?1:4) , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET ) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10)) , MISC_SHU_RODTENSTB_RODTENSTB_EXT ));
//[SV] //SHL, fix RODT rd_period low 1T issue
// @Darren, confirm MP settings w/ Chau-Wei Wang (Jason)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0) , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1) , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD ));
switch (A_D->DQ_P2S_RATIO)
{
case 4:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
case 8:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
case 16:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 3 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
default:mcSHOW_ERR_MSG(("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO));
}
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id));
}
static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ONCE ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_1RANK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN ) \
| P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \
| P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id));
}
static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 RD_DBI_EN = 1;//TODO
U8 WR_DBI_EN = 1;//TODO
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n", group_id));
if(LPDDR4_EN_S)
{
LP4_DRAM_CONFIG_T LP4_temp;
memset((void *)&LP4_temp, 0, sizeof(LP4_temp));
LP4_DRAM_config(DFS(group_id)->data_rate,&LP4_temp);
RD_DBI_EN = LP4_temp.DBI_RD;
WR_DBI_EN = LP4_temp.DBI_WR;
}
#if __LP5_COMBO__
else
{//TODO LPDDR5 and other dram type not ready
LP5_DRAM_CONFIG_T LP5_temp;
memset((void *)&LP5_temp, 0, sizeof(LP5_temp));
LP5_DRAM_config(DFS(group_id),&LP5_temp);
RD_DBI_EN = LP5_temp.DBI_RD;
WR_DBI_EN = LP5_temp.DBI_WR;
}
#endif
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0 ) \
| P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1 ) \
| P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(WR_DBI_EN, SHU_TX_SET0_DBIWR ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n", group_id));
}
//TODO LPDDR5
static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
U8 HWSET_MR13_OP_Value =0;
U8 HWSET_VRCG_OP_Value =0;
U8 HWSET_MR2_OP_Value =0;
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n", group_id));
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
if(LPDDR4_EN_S)
{
LP4_DRAM_CONFIG_T LP4_temp;
memset((void *)&LP4_temp, 0, sizeof(LP4_temp));
LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp);
HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable
HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6);
HWSET_MR2_OP_Value = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7);
} else {
mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers."));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(HWSET_MR13_OP_Value, SHU_HWSET_MR13_HWSET_MR13_OP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(HWSET_VRCG_OP_Value, SHU_HWSET_VRCG_HWSET_VRCG_OP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(0xb , SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2 ), P_Fld(HWSET_MR2_OP_Value , SHU_HWSET_MR2_HWSET_MR2_OP ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG6(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
}
#if __LP5_COMBO__
void DIG_CONFG_SHU_LP5_WCK(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
U8 BYTEMODE_EN=0;//TODO
U8 READ_DBI=0;
U8 DVFSC_DIS=0;
U8 WCK_offset_by_UI=0;
U8 tWCKENL_WR=0;
U8 tWCKPRE_WR_Static=0;
U8 tWCKENL_RD_DBION=0;
U8 tWCKENL_RD_DBIOFF=0;
U8 tWCKPRE_RD_Static=0;
U8 tWCKENL_FS=0;
U8 tWCKPRE_FS_Static=0;
U8 WCK_WR_MCK=0;
U8 WCK_RD_MCK=0;
U8 WCK_FS_MCK=0;
U8 WCK_WR_UI=0;
U8 WCK_RD_UI=0;
U8 WCK_FS_UI=0;
U8 irank = 0;
U8 ui_ratio = 2;
//write and FS
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =2;tWCKENL_FS =0;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =4;tWCKENL_FS =1;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =1;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =2;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_WR =3;tWCKPRE_WR_Static =3;tWCKENL_FS =2;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
//read
if(DVFSC_DIS == 1)
{
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?3:1;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:2;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:5;tWCKENL_RD_DBION =7;tWCKPRE_RD_Static =4;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?2:1;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:1;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =BYTEMODE_EN?5:4;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?5:4;tWCKENL_RD_DBION =BYTEMODE_EN?6:5;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?6:5;tWCKENL_RD_DBION =BYTEMODE_EN?7:6;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?8:7;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?9:7;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?8:7;tWCKENL_RD_DBION =BYTEMODE_EN?10:8;tWCKPRE_RD_Static=4;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
} else {
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:0;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =2;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?1:0;tWCKENL_RD_DBION =1;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =1;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
}
//=====================================
//Algrithm
//=====================================
WCK_offset_by_UI = (DFS(group_id)->DQ_P2S_RATIO==4) ? 0 :
(DFS(group_id)->DQ_P2S_RATIO==8) ? ((DFS(group_id)->CKR==4) ? 1 : -5) :
(DFS(group_id)->DQ_P2S_RATIO==16) ? -5 : 0;
WCK_WR_UI = ((tWCKENL_WR + tWCKPRE_WR_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
WCK_RD_UI = (((READ_DBI?tWCKENL_RD_DBION:tWCKENL_RD_DBIOFF) + tWCKPRE_RD_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
WCK_FS_UI = ((tWCKENL_FS + tWCKPRE_FS_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
//=====================================
//setting
//=====================================
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
for(irank = RANK_0; irank < RANK_MAX; irank++)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK), P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) \
| P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_MCK), P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) \
| P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_MCK), P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) \
| P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI) , P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B0_UI ) \
| P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B1_UI ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_UI) , P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B0_UI ) \
| P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B1_UI ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_UI) , P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B0_UI ) \
| P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B1_UI ));
}
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
}
#endif
//=================================================
//Jump ratio calculate and setting
//------------------------------------------------
//notice: 400 800 not support tracking TODO
// should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition
//
//================================================
#if 0
void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
{
int tar;
int ratio = 32;
int result[DFS_GROUP_NUM];
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id));
for(tar = 0; tar<DFS_GROUP_NUM;tar++)
{
if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking
{
result[tar] = 0;
}
else
{
result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup
}
mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]));
}
//=============================
//setting
//=============================
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld( result[0] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \
| P_Fld( result[1] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) \
| P_Fld( result[2] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) \
| P_Fld( result[3] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET1), P_Fld( result[4] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4) \
| P_Fld( result[5] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5) \
| P_Fld( result[6] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6) \
| P_Fld( result[7] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET2), P_Fld( result[8] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8) \
| P_Fld( result[9] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id));
}
#endif
static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
DIG_CONFIG_SHUF_DVFSWLRL(p,ch_id,group_id);
//TX_RX_jumpratio_calculate(p,ch_id,group_id);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DVFSDLL ) , P_Fld((LPDDR4_EN_S==1)?0x37:0x37 , MISC_SHU_DVFSDLL_R_DLL_IDLE )\
| P_Fld((LPDDR4_EN_S==1)?0x4d:0x37 , MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE )\
| P_Fld( ana_top_p.ALL_SLAVE_EN , MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL )\
| P_Fld( 0 , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL ));
}
//====================================
// Digital shuffle configuration entry
//------------------------------------
//Notice:
//
//====================================
void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id);
DIG_CONFIG_SHUF_IMP(p,ch_id,group_id);
DIG_CONFIG_SHUF_RXINPUT(p,ch_id,group_id);
DIG_CONFIG_SHUF_MISC_FIX(p,ch_id,group_id);
DIG_CONFIG_SHUF_DQSGRETRY(p,ch_id,group_id);
DIG_CONFIG_SHUF_DBI(p,ch_id,group_id);
DIG_CONFIG_DVFS_DEPENDENCE(p,ch_id,group_id);
}
#if 0
static void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
U8 backup_ch_id = p->channel;
U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
//notice here. Replace the A_D A_T with new frequency auto-generation
ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate);
ANA_CLK_DIV_config(A_D,DFS(group_id));
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly
ANA_Config_shuffle(p,A_T,group_id);
DIG_CONFIG_SHUF(p,ch_id,group_id);
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
}
#endif
#if FOR_DV_SIMULATION_USED
void DPI_OTHER_GP_INIT(U32 ch_id, U32 group_id)
{
mysetscope();
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
OTHER_GP_INIT(DramcConfig,ch_id,group_id);
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
conf_to_sram_sudo(0,group_id,1);
conf_to_sram_sudo(1,group_id,1);
//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
//DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_B);
//DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
//DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
#endif

321
src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c Normal file
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@@ -0,0 +1,321 @@
#include "dramc_dv_init.h"
DRAM_TYPE_T MEM_TYPE = LPDDR4;
LP4_DRAM_CONFIG_T LP4_INIT;
LP5_DRAM_CONFIG_T LP5_INIT;
ANA_top_config_T ana_top_p;
ANA_DVFS_CORE_T ANA_option;
DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
DRAMC_SUBSYS_CONFIG_T DV_p;
void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
{
// tr-> DLL_ASYNC_EN = 0 ; //from DV random
// tr-> NEW_RANK_MODE = 1 ; //from DV random
// tr-> DLL_IDLE_MODE = 1 ; //from DV random
// tr-> LP45_APHY_COMB_EN= 1 ; //from DV define
// tr-> NEW_8X_MODE = 1 ;
tr->ALL_SLAVE_EN = (data_rate <= 1866)?1:0;
if(LPDDR5_EN_S == 1)
{
tr->TX_ODT_DIS = (data_rate <=3200) ? 1 : 0 ;
} else {
tr->TX_ODT_DIS = (data_rate <=2400) ? 1 : 0 ;
}
mcSHOW_DBG_MSG6(("=================================== \n"));
mcSHOW_DBG_MSG6(("ANA top config\n" ));
mcSHOW_DBG_MSG6(("=================================== \n"));
mcSHOW_DBG_MSG6(("DLL_ASYNC_EN = %2d\n",tr->DLL_ASYNC_EN ));
mcSHOW_DBG_MSG6(("ALL_SLAVE_EN = %2d\n",tr->ALL_SLAVE_EN ));
mcSHOW_DBG_MSG6(("NEW_RANK_MODE = %2d\n",tr->NEW_RANK_MODE ));
mcSHOW_DBG_MSG6(("DLL_IDLE_MODE = %2d\n",tr->DLL_IDLE_MODE ));
mcSHOW_DBG_MSG6(("LP45_APHY_COMB_EN = %2d\n",tr->LP45_APHY_COMB_EN));
mcSHOW_DBG_MSG6(("TX_ODT_DIS = %2d\n",tr->TX_ODT_DIS ));
mcSHOW_DBG_MSG6(("NEW_8X_MODE = %2d\n",tr->NEW_8X_MODE ));
mcSHOW_DBG_MSG6(("=================================== \n"));
}
void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
{
U32 SEMI_OPEN_FMIN = 300;
U32 SEMI_OPEN_FMAX = 500; //lp4 600
U32 PI_FMIN = 600;
U32 DQ_PICK;
U32 CA_PICK; //U
U32 CA_MCKIO; //S
U32 MCKIO_SEMI; //Q
U16 data_rate;
data_rate = dfs->data_rate;
tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO;
tr->CKR = dfs->CKR;
//tr->CA_P2S_RATIO
tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR;
//tr->DQ_CA_OPEN
tr->DQ_CA_OPEN = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0;
tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0);
tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN);
tr->CA_FULL_RATE = (tr->DQ_CA_OPEN == 1) ? ((tr->CKR>1)?1:0) : ((tr->DQ_SEMI_OPEN*tr->CA_SEMI_OPEN*(tr->CKR>>1)) + (( data_rate/(tr->CKR*2) < PI_FMIN) ? (1-tr->CA_SEMI_OPEN) : 0 ));
tr->DQ_CKDIV4_EN = ( tr->DQ_SEMI_OPEN == 1) ? DONT_CARE_VALUE : ((( (data_rate/2) < 1200 ) ? 1 : 0 ) * (1-tr->DQ_CA_OPEN)) ;
CA_MCKIO = (data_rate/(tr->CKR*2))*(1+tr->CA_FULL_RATE);
DQ_PICK = (tr->DQ_SEMI_OPEN == 1) ? 0 : (data_rate/2) ;
CA_PICK = (tr->CA_SEMI_OPEN == 1) ? CA_MCKIO*2 : ((CA_MCKIO>=PI_FMIN) ? CA_MCKIO : (( CA_MCKIO >= (PI_FMIN/2) ) ? CA_MCKIO*2 : CA_MCKIO *4 ));
tr->CA_CKDIV4_EN = ((CA_PICK < 1200 ) ? 1 : 0 ) * ( 1- tr->DQ_CA_OPEN) ;
tr->CA_PREDIV_EN = (data_rate >= 4800) ? 1 : 0 ;
#if SA_CONFIG_EN
if(LPDDR4_EN_S)
{
// @Darren, for LP4 8PH Delay
if (data_rate <= 1866)
tr->PH8_DLY = 0;
else if (data_rate <= 2400)
tr->PH8_DLY = 0x12;
else if (data_rate <= 3200)
tr->PH8_DLY = 0xd;
else if (data_rate <= 4266)
tr->PH8_DLY = 0x8;
else
tr->PH8_DLY = 0x7;
}
else
#endif
{
tr->PH8_DLY = ((tr->DQ_CA_OPEN == 0) && (tr->DQ_SEMI_OPEN == 0) && (tr->DQ_CKDIV4_EN == 0)) ? ( (1000000>>4)/data_rate -4) : DONT_CARE_VALUE;
}
MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO;
tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved
tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE;
tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE;
tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved
//tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK.
tr->DQ_TRACK_CA_EN = 0 ;
tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1));
#if SA_CONFIG_EN
//de-sense
if(data_rate==2400)
tr->PLL_FREQ = 2366; //DDR2366
else if(data_rate==1200)
tr->PLL_FREQ = 2288; //DDR1144
else if(data_rate==3200 || data_rate==1600)
tr->PLL_FREQ = 3068; //DDR3068 DDR1534
else if(data_rate==800)
tr->PLL_FREQ = 3016; //DDR754
else if(data_rate==400)
tr->PLL_FREQ = 1600; //DDR400 1600/div4
#endif
tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use
tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32;
mcSHOW_DBG_MSG6(("=================================== \n"));
mcSHOW_DBG_MSG6(("data_rate = %4d\n" ,data_rate ));
mcSHOW_DBG_MSG6(("CKR = %1d\n" ,tr->CKR ));
mcSHOW_DBG_MSG6(("DQ_P2S_RATIO = %1d\n" ,tr->DQ_P2S_RATIO ));
mcSHOW_DBG_MSG6(("=================================== \n"));
mcSHOW_DBG_MSG6(("CA_P2S_RATIO = %1d\n" ,tr->CA_P2S_RATIO ));
mcSHOW_DBG_MSG6(("DQ_CA_OPEN = %1d\n" ,tr->DQ_CA_OPEN ));
mcSHOW_DBG_MSG6(("DQ_SEMI_OPEN = %1d\n" ,tr->DQ_SEMI_OPEN ));
mcSHOW_DBG_MSG6(("CA_SEMI_OPEN = %1d\n" ,tr->CA_SEMI_OPEN ));
mcSHOW_DBG_MSG6(("CA_FULL_RATE = %1d\n" ,tr->CA_FULL_RATE ));
mcSHOW_DBG_MSG6(("DQ_CKDIV4_EN = %1d\n" ,tr->DQ_CKDIV4_EN ));
mcSHOW_DBG_MSG6(("CA_CKDIV4_EN = %1d\n" ,tr->CA_CKDIV4_EN ));
mcSHOW_DBG_MSG6(("CA_PREDIV_EN = %1d\n" ,tr->CA_PREDIV_EN ));
mcSHOW_DBG_MSG6(("PH8_DLY = %1d\n" ,tr->PH8_DLY ));
mcSHOW_DBG_MSG6(("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n" ,tr->SEMI_OPEN_CA_PICK_MCK_RATIO));
mcSHOW_DBG_MSG6(("DQ_AAMCK_DIV = %1d\n" ,tr->DQ_AAMCK_DIV ));
mcSHOW_DBG_MSG6(("CA_AAMCK_DIV = %1d\n" ,tr->CA_AAMCK_DIV ));
mcSHOW_DBG_MSG6(("CA_ADMCK_DIV = %1d\n" ,tr->CA_ADMCK_DIV ));
mcSHOW_DBG_MSG6(("DQ_TRACK_CA_EN = %1d\n" ,tr->DQ_TRACK_CA_EN ));
mcSHOW_DBG_MSG6(("CA_PICK = %2d\n" ,CA_PICK ));
mcSHOW_DBG_MSG6(("CA_MCKIO = %1d\n" ,CA_MCKIO ));
mcSHOW_DBG_MSG6(("MCKIO_SEMI = %1d\n" ,MCKIO_SEMI ));
mcSHOW_DBG_MSG6(("PLL_FREQ = %1d\n" ,tr->PLL_FREQ ));
mcSHOW_DBG_MSG6(("DQ_UI_PI_RATIO = %1d\n" ,tr->DQ_UI_PI_RATIO ));
mcSHOW_DBG_MSG6(("CA_UI_PI_RATIO = %1d\n" ,tr->CA_UI_PI_RATIO ));
mcSHOW_DBG_MSG6(("=================================== \n"));
}
void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
{
U8 gp_id;
tr->SRAM_EN = 1;
tr->MD32_EN = 1;
tr->a_cfg = &ana_top_p;
tr->a_opt = &ANA_option;
tr->lp4_init = &LP4_INIT;
tr->lp5_init = &LP5_INIT;
for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
{
tr->DFS_GP[gp_id] = &DFS_TOP[gp_id];
}
if(LPDDR4_EN_S)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[2])->data_rate = 2400; (tr->DFS_GP[2])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[3])->data_rate = 1866; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[4])->data_rate = 1600; (tr->DFS_GP[4])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[5])->data_rate = 1200; (tr->DFS_GP[5])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[6])->data_rate = 800 ; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[7])->data_rate = 400 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[8])->data_rate = 4266; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[9])->data_rate = 1600; (tr->DFS_GP[9])->DQ_P2S_RATIO = 4;
for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
{
(tr->DFS_GP[gp_id])->CKR = 1;
(tr->DFS_GP[gp_id])->DQSIEN_MODE = 1;
}
#if 0//DV_CONFIG_EN==1
tr->lp4_init->LP4Y_EN = DUT_p.LP4Y_EN ;
tr->lp4_init->WR_PST = DUT_p.LP4_WR_PST ;
tr->lp4_init->OTF = DUT_p.LP4_OTF ;
tr->a_cfg->NEW_8X_MODE = DUT_p.NEW_8X_MODE ;
tr->a_cfg->LP45_APHY_COMB_EN = 1 ;
tr->a_cfg->DLL_IDLE_MODE = DUT_p.DLL_IDLE_MODE ;
tr->a_cfg->NEW_RANK_MODE = DUT_p.NEW_RANK_MODE ;
tr->a_cfg->DLL_ASYNC_EN = DUT_p.DLL_ASYNC_EN ;
tr->MD32_EN = DUT_p.MD32_EN ;
tr->SRAM_EN = DUT_p.SRAM_EN ;
tr->GP_NUM = DUT_p.GP_NUM ;
for(gp_id = 0; gp_id < DV_p.GP_NUM; gp_id++)
{
tr->DFS_GP[gp_id]->data_rate = DUT_shu_p[gp_id].data_rate ;
tr->DFS_GP[gp_id]->DQSIEN_MODE = DUT_shu_p[gp_id].DQSIEN_MODE ;
tr->DFS_GP[gp_id]->DQ_P2S_RATIO = DUT_shu_p[gp_id].DQ_P2S_RATIO;
tr->DFS_GP[gp_id]->CKR = DUT_shu_p[gp_id].CKR ;
}
#endif
#if SA_CONFIG_EN
tr->lp4_init->EX_ROW_EN[0] = p->u110GBEn[RANK_0] ;
tr->lp4_init->EX_ROW_EN[1] = p->u110GBEn[RANK_1] ;
tr->lp4_init->BYTE_MODE[0] = 0 ;
tr->lp4_init->BYTE_MODE[1] = 0 ;
tr->lp4_init->LP4Y_EN = 0;//DUT_p.LP4Y_EN ;
tr->lp4_init->WR_PST = 1;//DUT_p.LP4_WR_PST ;
tr->lp4_init->OTF = 1;//DUT_p.LP4_OTF ;
tr->a_cfg->NEW_8X_MODE = 1;//DUT_p.NEW_8X_MODE ;
tr->a_cfg->LP45_APHY_COMB_EN = 1 ;
tr->a_cfg->DLL_IDLE_MODE = 1;//DUT_p.DLL_IDLE_MODE ;
tr->a_cfg->NEW_RANK_MODE = 1;//DUT_p.NEW_RANK_MODE ;
tr->a_cfg->DLL_ASYNC_EN = 0;//DUT_p.DLL_ASYNC_EN ;
tr->MD32_EN = 0;//DUT_p.MD32_EN ;
tr->SRAM_EN = 1;//DUT_p.SRAM_EN ;
tr->GP_NUM = 10;//DUT_p.GP_NUM ;
if(p->freq_sel==LP4_DDR4266)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR3733)
{
(tr->DFS_GP[0])->data_rate = 3733; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR3200)
{
(tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR2400)
{
(tr->DFS_GP[0])->data_rate = 2400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1866)
{
(tr->DFS_GP[0])->data_rate = 1866; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1600)
{
(tr->DFS_GP[0])->data_rate = 1600; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1200)
{
(tr->DFS_GP[0])->data_rate = 1200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR800)
{
(tr->DFS_GP[0])->data_rate = 800; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
}
else if(p->freq_sel==LP4_DDR400)
{
(tr->DFS_GP[0])->data_rate = 400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
}
#endif
//==============================================
//Oterwise, SA should rebuild Top configuration.
//==============================================
LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init);
}
//TODO for LPDDR5
//data_rate DQ_P2S_RATIO
//[4800:6400] 16
//[1600:4800) 8
//[400 :1600] 4
//=========================
//data_rate CKR
//[3733:6400] 4
//[400 :3733) 2
#if __LP5_COMBO__
else if (MEM_TYPE == LPDDR5)
{
#if SA_CONFIG_EN
if(p->freq_sel==LP5_DDR4266)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else if(p->freq_sel==LP5_DDR5500)
{
(tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else
{
(tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1;
}
#else
(tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1;
#endif
(tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1;
(tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1;
(tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1;
(tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1;
(tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1;
(tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1;
(tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1;
(tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1;
(tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1;
LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init);
}
#endif
ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
mcSHOW_DBG_MSG6(("=================================== \n"));
mcSHOW_DBG_MSG6(("memory_type:%s \n",LPDDR5_EN_S?"LPDDR5":"LPDDR4" ));
mcSHOW_DBG_MSG6(("GP_NUM : %1d \n",tr->GP_NUM ));
mcSHOW_DBG_MSG6(("SRAM_EN : %1d \n",tr->SRAM_EN ));
mcSHOW_DBG_MSG6(("MD32_EN : %1d \n",tr->MD32_EN ));
mcSHOW_DBG_MSG6(("=================================== \n"));
#if DUMP_ALLSUH_RG
mcSHOW_DBG_MSG(("[DUMPLOG] %d DQ_MCK_UI_RATIO=%d, DQ_UI_PI_RATIO=%d, CA_UI_PI_RATIO=%d\n", p->frequency * 2, vGet_Div_Mode(p) == DIV8_MODE ? 8 : 4, tr->a_opt->DQ_UI_PI_RATIO, tr->a_opt->CA_UI_PI_RATIO));
#endif
}

414
src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c Normal file
View File

@@ -0,0 +1,414 @@
#include "dramc_dv_init.h"
//DRAM LP4 initial configuration
void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0;//TODO
tr->BYTE_MODE[1] = 0;//TODO
#if 0 // @Darren, remove it
#if SA_CONFIG_EN
tr->EX_ROW_EN[0] = 0;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
#else
tr->EX_ROW_EN[0] = 1;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
#endif
#endif
tr->MR_WL = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate);
tr->MR_RL = tr->MR_WL;
tr->BL = 2;
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (data_rate>=2667)?1:0; //TODO
#if SA_CONFIG_EN
tr->DBI_WR = 0;
tr->DBI_RD = 0;
#else
tr->DBI_WR = (data_rate>=2667)?1:0;
tr->DBI_RD = (data_rate>=2667)?1:0;
#endif
// tr->DMI = 1;
tr->OTF = 1;
#if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION)
tr->LP4Y_EN = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y
#else
tr->LP4Y_EN = 0;
#endif
tr->WORK_FSP = (data_rate>=2667)?1:0;
mcSHOW_DBG_MSG2(("=================================== \n"));
mcSHOW_DBG_MSG2(("LPDDR4 DRAM CONFIGURATION\n" ));
mcSHOW_DBG_MSG2(("=================================== \n"));
// mcSHOW_DBG_MSG(("BYTE_MODE = B%1b\n",tr->BYTE_MODE));
mcSHOW_DBG_MSG2(("EX_ROW_EN[0] = 0x%1x\n",tr->EX_ROW_EN[0]));
mcSHOW_DBG_MSG2(("EX_ROW_EN[1] = 0x%1x\n",tr->EX_ROW_EN[1]));
mcSHOW_DBG_MSG2(("LP4Y_EN = 0x%1x\n",tr->LP4Y_EN ));
mcSHOW_DBG_MSG2(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
mcSHOW_DBG_MSG2(("WL = 0x%1x\n",tr->MR_WL ));
mcSHOW_DBG_MSG2(("RL = 0x%1x\n",tr->MR_RL ));
mcSHOW_DBG_MSG2(("BL = 0x%1x\n",tr->BL ));
mcSHOW_DBG_MSG2(("RPST = 0x%1x\n",tr->RPST ));
mcSHOW_DBG_MSG2(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
mcSHOW_DBG_MSG2(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
mcSHOW_DBG_MSG2(("WR_PST = 0x%1x\n",tr->WR_PST ));
mcSHOW_DBG_MSG2(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
mcSHOW_DBG_MSG2(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
// mcSHOW_DBG_MSG(("DMI = 0x%1x\n",tr->DMI ));
mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG2(("=================================== \n"));
}
//LP4 dram initial ModeRegister setting
U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL;
if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
else if ((data_rate<=3733) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
else if ((data_rate<=3200) && (data_rate > 2667)) {MR2_RLWL = 5 ;}
else if ((data_rate<=2667) && (data_rate > 2400)) {MR2_RLWL = 4 ;}
else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
else if ((data_rate<=1600) && (data_rate > 1200)) {MR2_RLWL = 2 ;}
else if ((data_rate<=1200) && (data_rate > 800 )) {MR2_RLWL = 2 ;}
else if ((data_rate<=800 ) && (data_rate > 400 )) {MR2_RLWL = 1 ;}
else if (data_rate<=400 ) {MR2_RLWL = 0 ;}
else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate));return -1;}
mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
return MR2_RLWL;
}
U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value)
{
U32 RL=0;
switch(MR_RL_field_value)
{
case 0: {RL = 6; break;}
case 1: {RL = ((DBI_EN == 1) ? 12 : 10); break;}
case 2: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ((DBI_EN == 1) ? 16 : 14); break;}
case 3: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 24 : 22 ) : ((DBI_EN == 1) ? 22 : 20); break;}
case 4: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 30 : 28 ) : ((DBI_EN == 1) ? 28 : 24); break;}
case 5: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 36 : 32 ) : ((DBI_EN == 1) ? 32 : 28); break;}
case 6: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 40 : 36 ) : ((DBI_EN == 1) ? 36 : 32); break;}
case 7: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 44 : 40 ) : ((DBI_EN == 1) ? 40 : 36); break;}
default:{mcSHOW_ERR_MSG(("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value));}
}
mcSHOW_DBG_MSG(("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL));
return RL;
}
U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
{
U32 WL=0;
switch(MR_WL_field_value)
{
case 0: {WL = 4; break;}
case 1: {WL = ((Version == 0) ? 6 : 8 ); break;}
case 2: {WL = ((Version == 0) ? 8 : 12 ); break;}
case 3: {WL = ((Version == 0) ? 10 : 18 ); break;}
case 4: {WL = ((Version == 0) ? 12 : 22 ); break;}
case 5: {WL = ((Version == 0) ? 14 : 26 ); break;}
case 6: {WL = ((Version == 0) ? 16 : 30 ); break;}
case 7: {WL = ((Version == 0) ? 18 : 34 ); break;}
default:{mcSHOW_ERR_MSG(("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value));}
}
mcSHOW_DBG_MSG(("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL));
return WL;
}
#if __LP5_COMBO__
U32 Get_RL_LP5_DVFSC_DIS( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
{
U32 RL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 6; break;}
case 1 : {RL = 8; break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 10 ) : 10); break;}
case 3 : {RL = ((BYTE_MODE_EN == 1) ? ( 14 ) : ((DBI_EN == 1) ? 14 : 12 )); break;}
case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ( 16 )); break;}
case 5 : {RL = ((BYTE_MODE_EN == 1) ? ( 20 ) : ((DBI_EN == 1) ? 20 : 18 )); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 3; break;}
case 1 : {RL = 4; break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 6 : 5 ) : ( 5 )); break;}
case 3 : {RL = ((BYTE_MODE_EN == 1) ? 7 : ((DBI_EN == 1) ? 7 : 6 )); break;}
case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 9 : 8 ) : ( 8 )); break;}
case 5 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 9 )); break;}
case 6 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 11 ) : ((DBI_EN == 1) ? 11 : 10)); break;}
case 7 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 13 ) : ((DBI_EN == 1) ? 13 : 12)); break;}
case 8 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 15 : 14 ) : ((DBI_EN == 1) ? 14 : 13)); break;}
case 9 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 17 : 16 ) : ((DBI_EN == 1) ? 16 : 15)); break;}
case 10: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 19 : 17 ) : ((DBI_EN == 1) ? 17 : 16)); break;}
case 11: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 20 : 18 ) : ((DBI_EN == 1) ? 18 : 17)); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
return RL;
}
U32 Get_RL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
{
U32 RL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 6; break;}
case 1 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 8 )); break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 12 ) : 12); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 3; break;}
case 1 : {RL = ((BYTE_MODE_EN == 1) ? 5 : ((DBI_EN == 1) ? 4 : 5 )); break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 7 : 6 ) : 6); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
return RL;
}
//LPDDR5 write Latency Version B not implemented --TODO
U32 Get_WL_LP5_DVFSC_DIS( U8 MR_RL_field_value,U8 BYTE_MODE_EN,U8 CKR)
{
U32 WL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 4; break;}
case 1 : {WL = 4; break;}
case 2 : {WL = 6; break;}
case 3 : {WL = 8; break;}
case 4 : {WL = 8; break;}
case 5 : {WL = 10; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 2; break;}
case 1 : {WL = 2; break;}
case 2 : {WL = 3; break;}
case 3 : {WL = 4; break;}
case 4 : {WL = 4; break;}
case 5 : {WL = 5; break;}
case 6 : {WL = 6; break;}
case 7 : {WL = 6; break;}
case 8 : {WL = 7; break;}
case 9 : {WL = 8; break;}
case 10: {WL = 9; break;}
case 11: {WL = 9; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
return WL;
}
//LPDDR5 write Latency Version B not implemented --TODO
U32 Get_WL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 BYTE_MODE_EN,U8 CKR)
{
U32 WL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 4; break;}
case 1 : {WL = 4; break;}
case 2 : {WL = 6; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 2; break;}
case 1 : {WL = 2; break;}
case 2 : {WL = 3; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
return WL;
}
//LP5 dram initial ModeRegister setting
U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL=0;
if ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;}
else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;}
else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9 ;}
else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8 ;}
else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5 ;}
else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2 ;}
else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
return MR2_RLWL;
}
void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0 ;
tr->BYTE_MODE[1] = 0 ;
tr->EX_ROW_EN[0] = 0 ;
tr->EX_ROW_EN[1] = 0 ;
tr->MR_WL = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate);
tr->MR_RL = tr->MR_WL;
tr->BL = 2;
tr->CK_Mode = (dfs_tr->data_rate>=2133)?0:1; //0:diff 1:SE
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (dfs_tr->data_rate>=3200)?1:0 ;
#if SA_CONFIG_EN
tr->DBI_WR = 0;
#if LP5_DDR4266_RDBI_WORKAROUND
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#else
tr->DBI_RD = 0;
#endif
#else
tr->DBI_WR = (dfs_tr->data_rate>=3733)?1:0 ;
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#endif
tr->DMI = 1;
tr->OTF = 1;
tr->WCK_PST = (dfs_tr->data_rate>=3733)?1:0 ;
tr->RDQS_PST = 0;
tr->CA_ODT = 0;
tr->DQ_ODT = (dfs_tr->data_rate>=3733)?3:0 ;
tr->CKR = (dfs_tr->CKR==4)?0:1;
tr->WCK_ON = 0; //TODO
#if SA_CONFIG_EN
#if WCK_LEVELING_FM_WORKAROUND
tr->WCK_FM = 0;
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
tr->WCK_ODT = (dfs_tr->CKR==4)?3:0;
tr->DVFSQ = (dfs_tr->data_rate>=3733)?0:1;
tr->DVFSC = (dfs_tr->data_rate>=2133)?0:1;
tr->RDQSmode[0] = EN_both;//TODO --RK0 have to EN_t if SE enable
tr->RDQSmode[1] = EN_both;//TODO --RK1 have to EN_c if SE enable
tr->WCKmode[0] = (dfs_tr->data_rate>=1600)?0:1;
tr->WCKmode[1] = (dfs_tr->data_rate>=1600)?0:2;
tr->RECC = 0;//TODO
tr->WECC = 0;//TODO
tr->BankMode = (dfs_tr->data_rate>=3733)?BG4BK4:BK16;
tr->WORK_FSP = 0;//TODO
switch (dfs_tr->DQSIEN_MODE)
{
case 1: {tr->RDQS_PRE = 0;break;}
case 2: {tr->RDQS_PRE = 1;break;}
case 3: {tr->RDQS_PRE = 3;break;}
case 6: {tr->RDQS_PRE = 1;break;}
case 7: {tr->RDQS_PRE = 3;break;}
default : {mcSHOW_ERR_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
}
mcSHOW_DBG_MSG2(("=================================== \n"));
mcSHOW_DBG_MSG2(("LPDDR5 DRAM CONFIGURATION\n" ));
mcSHOW_DBG_MSG2(("=================================== \n"));
mcSHOW_DBG_MSG2(("MR_WL = 0x%1x\n",tr->MR_WL ));
mcSHOW_DBG_MSG2(("MR_RL = 0x%1x\n",tr->MR_RL ));
mcSHOW_DBG_MSG2(("BL = 0x%1x\n",tr->BL ));
mcSHOW_DBG_MSG2(("CK_Mode = 0x%1x\n",tr->CK_Mode ));
mcSHOW_DBG_MSG2(("RPST = 0x%1x\n",tr->RPST ));
mcSHOW_DBG_MSG2(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
mcSHOW_DBG_MSG2(("RDQS_PRE = 0x%1x\n",tr->RDQS_PRE ));
mcSHOW_DBG_MSG2(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
mcSHOW_DBG_MSG2(("WR_PST = 0x%1x\n",tr->WR_PST ));
mcSHOW_DBG_MSG2(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
mcSHOW_DBG_MSG2(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
mcSHOW_DBG_MSG2(("DMI = 0x%1x\n",tr->DMI ));
mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG2(("WCK_PST = 0x%1x\n",tr->WCK_PST ));
mcSHOW_DBG_MSG2(("RDQS_PST = 0x%1x\n",tr->RDQS_PST ));
mcSHOW_DBG_MSG2(("CA_ODT = 0x%1x\n",tr->CA_ODT ));
mcSHOW_DBG_MSG2(("DQ_ODT = 0x%1x\n",tr->DQ_ODT ));
mcSHOW_DBG_MSG2(("CKR = 0x%1x\n",tr->CKR ));
mcSHOW_DBG_MSG2(("WCK_ON = 0x%1x\n",tr->WCK_ON ));
mcSHOW_DBG_MSG2(("WCK_FM = 0x%1x\n",tr->WCK_FM ));
mcSHOW_DBG_MSG2(("WCK_ODT = 0x%1x\n",tr->WCK_ODT ));
mcSHOW_DBG_MSG2(("DVFSQ = 0x%1x\n",tr->DVFSQ ));
mcSHOW_DBG_MSG2(("DVFSC = 0x%1x\n",tr->DVFSC ));
mcSHOW_DBG_MSG2(("RDQSmode[0] = 0x%1x\n",tr->RDQSmode[0] ));
mcSHOW_DBG_MSG2(("RDQSmode[1] = 0x%1x\n",tr->RDQSmode[1] ));
mcSHOW_DBG_MSG2(("WCKmode[0] = 0x%1x\n",tr->WCKmode[0] ));
mcSHOW_DBG_MSG2(("WCKmode[1] = 0x%1x\n",tr->WCKmode[1] ));
mcSHOW_DBG_MSG2(("RECC = 0x%1x\n",tr->RECC ));
mcSHOW_DBG_MSG2(("WECC = 0x%1x\n",tr->WECC ));
mcSHOW_DBG_MSG2(("BankMode = 0x%1x\n",tr->BankMode ));
mcSHOW_DBG_MSG2(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
mcSHOW_DBG_MSG2(("=================================== \n"));
}
#endif

619
src/vendorcode/mediatek/mt8195/dramc/Hal_io.c Normal file
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@@ -0,0 +1,619 @@
/** @file hal_io.cpp
* hal_io.cpp provides functions of register access
*/
#include "x_hal_io.h"
#include "dramc_common.h"
#include "dramc_int_global.h"
#if __ETT__
#include <barriers.h>
#endif
#ifdef DUMP_INIT_RG_LOG_TO_DE
U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
#endif
#if FOR_DV_SIMULATION_USED
U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr)
{
U32 u4Offset = u4reg_addr & 0xffff;
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
U32 u4BaseAddr = 0;
if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL ||
u4reg_addr >= MAX_BASE_VIRTUAL)
{
return u4reg_addr;
}
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
{
if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register
{
if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
if (eRank == RANK_1)
{
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
{
if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
}
else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register
{
// 0x60~0xE0
if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x1E0~0x260
else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x360~0x3E0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x760~0x7E0
else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x8E0~0x960
else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xA60~0xAE0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xBE0~0xC60
else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
}
else if (u4RegType <= 1)// ChA/B Dramc NAO Register
{
if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
{
u4Offset += 0x100;
}
else if (u4Offset >= DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR &&
u4Offset <= DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR)
{
u4Offset += DRAMC_REG_NAO_RANK_OFFSET;
}
}
else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register
{
// PhyA/B NAO Register
if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END)
{
u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET;
}
}
}
switch (u4RegType)
{
case 0:
u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS;
break;
case 1:
u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS;
break;
case 2:
u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 3:
u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 4:
u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS;
break;
case 5:
u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS;
break;
case 6:
u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 7:
u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 8:
u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS;
break;
}
return (u4BaseAddr + u4Offset);
}
#else
static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr)
{
U32 u4Offset = u4reg_addr & 0xffff;
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0x1f;
U32 u4BaseAddr = 0;
if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL ||
u4reg_addr >= MAX_BASE_VIRTUAL)
{
return u4reg_addr;
}
if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
{
if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
else if (u4RegType >= 12 && u4RegType <= 15)// ChA/B Phy AO Register
{
if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
if (eRank == RANK_1)
{
if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register
{
if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
}
else if (u4RegType >= 12 && u4RegType <= 15)// PhyA/B AO Register
{
// 0x60~0xE0
if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x1E0~0x260
else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x360~0x3E0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x760~0x7E0
else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x8E0~0x960
else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xA60~0xAE0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xBE0~0xC60
else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
}
else if (u4RegType <= 3)// ChA/B Dramc NAO Register
{
if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
{
u4Offset += 0x100;
}
}
else if (u4RegType >= 8 && u4RegType <= 11) // PhyA/B NAO Register
{
// PhyA/B NAO Register
if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END)
{
u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET;
}
}
}
switch (u4RegType)
{
case 0:
u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS;
break;
case 1:
u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS;
break;
case 2:
u4BaseAddr = Channel_C_DRAMC_NAO_BASE_ADDRESS;
break;
case 3:
u4BaseAddr = Channel_D_DRAMC_NAO_BASE_ADDRESS;
break;
case 4:
u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 5:
u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 6:
u4BaseAddr = Channel_C_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 7:
u4BaseAddr = Channel_D_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 8:
u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS;
break;
case 9:
u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS;
break;
case 10:
u4BaseAddr = Channel_C_DDRPHY_NAO_BASE_ADDRESS;
break;
case 11:
u4BaseAddr = Channel_D_DDRPHY_NAO_BASE_ADDRESS;
break;
case 12:
u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 13:
u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 14:
u4BaseAddr = Channel_C_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 15:
u4BaseAddr = Channel_D_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 16:
u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS;
break;
case 17:
u4BaseAddr = Channel_B_DDRPHY_DPM_BASE_ADDRESS;
break;
}
return (u4BaseAddr + u4Offset);
}
#endif
//[FOR_CHROMEOS]
//inline U32 _u4Dram_Register_Read(U32 u4reg_addr)
inline U32 _u4Dram_Register_Read(U64 u4reg_addr)
{
U32 u4reg_value;
#if (!__ETT__) && (FOR_DV_SIMULATION_USED == 0)
dsb();
#endif
#if QT_GUI_Tool
ucDramRegRead_1(u4reg_addr, &u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
u4reg_value = register_read_c(u4reg_addr);
#else // real chip
u4reg_value = *((volatile unsigned int *)u4reg_addr);
#endif
return u4reg_value;
}
//-------------------------------------------------------------------------
/** ucDram_Register_Read
* DRAM register read (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param pu4reg_value Pointer of register read value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
// This function need to be porting by BU requirement
U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr)
{
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
#if (fcFOR_CHIP_ID == fc8195)
//ignore CH-B
if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
{
if(u4RegType%2!=0)
{
return 0;
}
}
#endif
u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
return _u4Dram_Register_Read(u4reg_addr);
}
//-------------------------------------------------------------------------
/** ucDram_Register_Write
* DRAM register write (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param u4reg_value register write value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
#if REG_ACCESS_NAO_DGB
#if (fcFOR_CHIP_ID == fcCervino)
U8 Check_RG_Not_AO(U32 u4reg_addr)
{
U8 RegNotAO = 0;
if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY))
{
}
else if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY + SHIFT_TO_CHB_ADDR))
{
}
else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC))
{
}
else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC + SHIFT_TO_CHB_ADDR))
{
}
else
{
RegNotAO = 1;
}
return RegNotAO;
}
#endif
#endif
//[FOR_CHROMEOS]
//inline void _ucDram_Register_Write(U32 u4reg_addr, U32 u4reg_value)
inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
{
#if QT_GUI_Tool
ucDramRegWrite_1(u4reg_addr, u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
register_write_c(u4reg_addr, u4reg_value);
#else // real chip
(*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip
#if !defined(__DPM__)
dsb();
#endif
#endif
#ifdef DUMP_INIT_RG_LOG_TO_DE
if (gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag == 1)
{
mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value));
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
mcDELAY_MS(1); // to receive log for log
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
}
#endif
#if REG_ACCESS_PORTING_DGB
if (RegLogEnable)
{
mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
}
#endif
}
//This function need to be porting by BU requirement
void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value)
{
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
#if (fcFOR_CHIP_ID == fc8195)
//ignore CH-B
if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL))
{
if(u4RegType%2!=0)
{
return;
}
}
#endif
#if __ETT__
//CheckDramcWBR(u4reg_addr);
#endif
//mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
_ucDram_Register_Write(u4reg_addr, u4reg_value);
}
void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
{
U32 u4Val;
U32 u4RegType = ((reg32 - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
//ignore CH-B
#if (fcFOR_CHIP_ID == fc8195)
if ((p->support_channel_num == CHANNEL_SINGLE) && (reg32 >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && reg32 <= MAX_BASE_VIRTUAL))
{
if(u4RegType%2!=0)
return;
}
#endif
reg32 = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32);
val32 &= msk32;
u4Val = _u4Dram_Register_Read(reg32);
u4Val = ((u4Val & ~msk32) | val32);
_ucDram_Register_Write(reg32, u4Val);
}
void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32)
{
U8 ii, u1AllCount;
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
U8 u1BCSupport = TRUE;
reg32 &= 0xffff; // remove channel information
u1AllCount = p->support_channel_num; // for all dramC and PHY
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
u1BCSupport = FALSE;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}
#if __ETT__
if (u1BCSupport && GetDramcBroadcast()==DRAMC_BROADCAST_ON)
{
mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
while (1);
}
#endif
for (ii = 0; ii < u1AllCount; ii++)
{
vIO32Write4B(reg32 + ((U32)ii << POS_BANK_NUM), val32);
}
}
void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
{
U32 u4Val, u4RegTmp;
U8 ii, u1AllCount;
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
U8 u1BCSupport = TRUE;
reg32 &= 0xffff; // remove channel information
u1AllCount = p->support_channel_num; // for all dramC and PHY
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
u1BCSupport = FALSE;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}
#if __ETT__
if (u1BCSupport && GetDramcBroadcast()==DRAMC_BROADCAST_ON)
{
mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
while (1);
}
#endif
for (ii = 0; ii < u1AllCount; ii++)
{
u4RegTmp = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32 + ((U32)ii << POS_BANK_NUM));
u4Val = _u4Dram_Register_Read(u4RegTmp);
u4Val = ((u4Val & ~msk32) | val32);
_ucDram_Register_Write(u4RegTmp, u4Val);
}
}

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src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c Normal file
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#include "dramc_dv_init.h"
void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank)
{
switch(rank)
{
case 0 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKEFIXON)); break;
case 1 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKE1FIXON)); break;
default: mcSHOW_ERR_MSG(("ERROR: CKE FIX ON error. Unexpected Rank \n"));
}
}
//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank);
static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
{
U8 temp_MRS_RESPONSE ;
mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p)));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), P_Fld(rank , SWCMD_CTRL0_MRSRK ) \
| P_Fld(reg_addr, SWCMD_CTRL0_MRSMA ) \
| P_Fld(reg_op , SWCMD_CTRL0_MRSOP ));
vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(1, SWCMD_EN_MRWEN));
temp_MRS_RESPONSE = 0 ;
do
{
temp_MRS_RESPONSE = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) ;
} while ( temp_MRS_RESPONSE != 1 );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(0, SWCMD_EN_MRWEN));
}
static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank)
{
U8 MR13 = 0;
MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/;
LP4_MRS(p, 13, MR13, rank);
}
//==================================
//uesage(constraint): DBI = 1 for FSPOP=1 if DBI=0 then FSP_OP =0
//==================================
static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank)
{
U8 MR1;
U8 MR2;
U8 MR3;
U8 MR51;
U8 MR11;
U8 MR12;
U8 MR14;
//default value for LP4 DRAM CONFIG
U8 nWR =5;
U8 WR_LEV =0;
U8 PDDS =5;
U8 PPRP =0;
U8 PU_CAL =0;
U8 WLS =0;
//Notice: DBI default = 0
//field & configuration adaption
MR1 = ((tr->RPST & 1)<<7) | ((nWR & 7)<<4) | ((tr->RD_PRE & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0);
MR2 = ((WR_LEV & 1)<<7) | ((WLS & 1)<<6) | ((tr->MR_WL & 7)<<3) | ((tr->MR_RL & 7)<<0);
MR3 = ((tr->DBI_WR & 1)<<7) | ((tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
MR51= ((tr->LP4Y_EN & 1)<<3) | ((tr->LP4Y_EN & 1)<<2) | ((tr->LP4Y_EN & 1)<<1);
if(tr->WORK_FSP == 0)
{
MR11 = 0x0;
MR14 = 0x5d;
}
else
{
MR11 = 0x04;
MR14 = 0x18;
}
MR12= 0x5d;
#if FSP1_CLKCA_TERM
if(p->dram_fsp == FSP_1)
MR12 = 0x20;
#endif
//temp workaround for global variable of MR
u1MR02Value[tr->WORK_FSP] = MR2;
u1MR03Value[tr->WORK_FSP] = MR3;
#if ENABLE_LP4_ZQ_CAL
DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency
#endif
mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank));
//first FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
else {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
mcDELAY_XNS(15); //TCKFSPE
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
LP4_MRS(p, 3, MR3 , rank);
LP4_MRS(p, 11, MR11 , rank);
LP4_MRS(p, 12, MR12 , rank);
LP4_MRS(p, 14, MR14 , rank);
if(tr->LP4Y_EN == 1) { LP4_MRS(p, 51, MR51, rank); }
mcDELAY_XNS(15); //TCKFSPX
//2nd FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
else {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
mcDELAY_XNS(15); //TCKFSPE
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
//reverse the DBI
MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
LP4_MRS(p, 3, MR3 , rank);
LP4_MRS(p, 11, MR11 , rank);
LP4_MRS(p, 12, MR12 , rank);
LP4_MRS(p, 14, MR14 , rank);
LP4_FSP_WR_or_OP(p, tr->WORK_FSP, tr->WORK_FSP, rank);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank));
}
void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
{
mcSHOW_DBG_MSG6(("============ LP4 DIFF to SE enter ============\n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \
| P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \
| P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \
| P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0) , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0) , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); //@Darren, debugging for DFS stress fail
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 ));
#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm
// for strong pull low and normal mode
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
#else
// for weak pull low mode only
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
#endif
mcSHOW_DBG_MSG6(("============ LP4 DIFF to SE exit ============\n"));
}
void LP4_DRAM_INIT(DRAMC_CTX_T *p)
{
U8 RANK;
#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround
DramcPowerOnSequence(p);
#endif
mcDELAY_XNS(200); //tINIT3 = 2ms for DV fastup to 200ns
for(RANK=0;RANK<2;RANK++)
{
CKE_FIX_ON(p,1,RANK);
mcDELAY_XNS(400); //tINIT5 fastup to 400ns
//step4 moderegister setting
lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK);
CKE_FIX_ON(p,0,RANK);
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh
}

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src/vendorcode/mediatek/mt8195/dramc/Makefile.inc Normal file
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romstage-y += emi.c
romstage-y += ANA_init_config.c
romstage-y += DIG_NONSHUF_config.c
romstage-y += DIG_SHUF_config.c
romstage-y += dramc_actiming.c
romstage-y += dramc_dv_freq_related.c
romstage-y += dramc_dvfs.c
romstage-y += dramc_lowpower.c
romstage-y += DRAM_config_collctioin.c
romstage-y += dramc_pi_basic_api.c
romstage-y += dramc_pi_calibration_api.c
romstage-y += dramc_pi_main.c
romstage-y += DRAMC_SUBSYS_config.c
romstage-y += dramc_top.c
romstage-y += dramc_tracking.c
romstage-y += dramc_utility.c
romstage-y += Hal_io.c
romstage-y += LP4_dram_init.c
romstage-y += dramc_debug.c
ramstage-y += emi.c

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#ifndef _ACTIMING_H
#define _ACTIMING_H
/***********************************************************************/
/* Includes */
/***********************************************************************/
#include "dramc_register.h"
//Definitions to enable specific freq's LP4 ACTiming support (To save code size)
#define SUPPORT_LP5_DDR6400_ACTIM 0
#define SUPPORT_LP5_DDR5500_ACTIM 0
#define SUPPORT_LP5_DDR4266_ACTIM 0
#define SUPPORT_LP5_DDR3200_ACTIM 0
#define SUPPORT_LP4_DDR4266_ACTIM 1
#define SUPPORT_LP4_DDR3733_ACTIM 1
#define SUPPORT_LP4_DDR3200_ACTIM 1
#define SUPPORT_LP4_DDR2667_ACTIM 0
#define SUPPORT_LP4_DDR2400_ACTIM 1
#define SUPPORT_LP4_DDR1866_ACTIM 1
#define SUPPORT_LP4_DDR1600_ACTIM 1
#define SUPPORT_LP4_DDR1333_ACTIM 0
#define SUPPORT_LP4_DDR1200_ACTIM 1
#define SUPPORT_LP4_DDR800_ACTIM 1
#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
#define SUPPORT_LP4_DDR400_ACTIM 1
#else
#define SUPPORT_LP4_DDR400_ACTIM 0
#endif
/* Used to keep track the total number of LP4 ACTimings */
/* Since READ_DBI is enable/disabled using preprocessor C define
* -> Save code size by excluding unneeded ACTimingTable entries
* Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1))
* Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used)
*/
typedef enum
{
#if SUPPORT_LP4_DDR4266_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0,
AC_TIME_LP4_NORM_DDR4266_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF,
AC_TIME_LP4_NORM_DDR4266_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR3733_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR3733_RDBI_ON,
AC_TIME_LP4_NORM_DDR3733_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF,
AC_TIME_LP4_NORM_DDR3733_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR3200_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR3200_RDBI_ON,
AC_TIME_LP4_NORM_DDR3200_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF,
AC_TIME_LP4_NORM_DDR3200_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR2667_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR2667_RDBI_ON,
AC_TIME_LP4_NORM_DDR2667_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF,
AC_TIME_LP4_NORM_DDR2667_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR2400_ACTIM
AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF,
AC_TIME_LP4_NORM_DDR2400_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1866_ACTIM
AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1866_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1600_ACTIM
AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1600_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1333_ACTIM
AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1333_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1200_ACTIM
AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1200_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR800_ACTIM
AC_TIME_LP4_BYTE_DDR800_RDBI_OFF,
AC_TIME_LP4_NORM_DDR800_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR400_ACTIM
AC_TIME_LP4_BYTE_DDR400_RDBI_OFF,
AC_TIME_LP4_NORM_DDR400_RDBI_OFF,
#endif
AC_TIMING_NUMBER_LP4
} AC_TIMING_LP4_COUNT_TYPE_T;
#if (__LP5_COMBO__)
/* Used to keep track the total number of LP5 ACTimings */
typedef enum
{
#if SUPPORT_LP5_DDR6400_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0,
AC_TIME_LP5_NORM_DDR6400_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF,
AC_TIME_LP5_NORM_DDR6400_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR5500_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR5500_RDBI_ON,
AC_TIME_LP5_NORM_DDR5500_RDBI_ON,
#else
AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF,
AC_TIME_LP5_NORM_DDR5500_RDBI_OFF,
#endif
#endif
#if SUPPORT_LP5_DDR4266_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR4266_RDBI_ON,
AC_TIME_LP5_NORM_DDR4266_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF,
AC_TIME_LP5_NORM_DDR4266_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR3200_ACTIM
AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF,
AC_TIME_LP5_NORM_DDR3200_RDBI_OFF,
#endif
AC_TIMING_NUMBER_LP5
} AC_TIMING_LP5_COUNT_TYPE_T;
#else
#define AC_TIMING_NUMBER_LP5 0
#endif
/* ACTiming struct declaration (declared here due Fld_wid for each register type)
* Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()
* Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters)
*/
typedef struct _ACTime_T_LP4
{
U8 dramType, cbtMode, readDBI;
U8 DivMode;
U16 freq;
U8 readLat, writeLat;
U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
U8 tras;
U8 trp;
U8 trpab;
U8 trc;
U8 trfc;
U8 trfcpb;
U8 txp;
U8 trtp;
U8 trcd;
U8 twr;
U8 twtr;
U8 tpbr2pbr;
U8 tpbr2act;
U8 tr2mrw;
U8 tw2mrw;
U8 tmrr2mrw;
U8 tmrw;
U8 tmrd;
U8 tmrwckel;
U8 tpde;
U8 tpdx;
U8 tmrri;
U8 trrd;
U8 trrd_4266;
U8 tfaw;
U8 tfaw_4266;
U8 trtw_odt_off;
U8 trtw_odt_on;
U16 txrefcnt;
U8 tzqcs;
U8 xrtw2w_new_mode;
U8 xrtw2w_old_mode;
U8 xrtw2r_odt_on;
U8 xrtw2r_odt_off;
U8 xrtr2w_odt_on;
U8 xrtr2w_odt_off;
U8 xrtr2r_new_mode;
U8 xrtr2r_old_mode;
U8 tr2mrr;
U8 vrcgdis_prdcnt;
U8 hwset_mr2_op;
U8 hwset_mr13_op;
U8 hwset_vrcg_op;
U8 trcd_derate;
U8 trc_derate;
U8 tras_derate;
U8 trpab_derate;
U8 trp_derate;
U8 trrd_derate;
U8 trtpd;
U8 twtpd;
U8 tmrr2w_odt_off;
U8 tmrr2w_odt_on;
U8 ckeprd;
U8 ckelckcnt;
U8 zqlat2;
//DRAMC_REG_SHU_AC_TIME_05T ===================================
U8 tras_05T;
U8 trp_05T;
U8 trpab_05T;
U8 trc_05T;
U8 trfc_05T;
U8 trfcpb_05T;
U8 txp_05T;
U8 trtp_05T;
U8 trcd_05T;
U8 twr_05T;
U8 twtr_05T;
U8 tpbr2pbr_05T;
U8 tpbr2act_05T;
U8 tr2mrw_05T;
U8 tw2mrw_05T;
U8 tmrr2mrw_05T;
U8 tmrw_05T;
U8 tmrd_05T;
U8 tmrwckel_05T;
U8 tpde_05T;
U8 tpdx_05T;
U8 tmrri_05T;
U8 trrd_05T;
U8 trrd_4266_05T;
U8 tfaw_05T;
U8 tfaw_4266_05T;
U8 trtw_odt_off_05T;
U8 trtw_odt_on_05T;
U8 trcd_derate_05T;
U8 trc_derate_05T;
U8 tras_derate_05T;
U8 trpab_derate_05T;
U8 trp_derate_05T;
U8 trrd_derate_05T;
U8 trtpd_05T;
U8 twtpd_05T;
} ACTime_T_LP4;
typedef struct _ACTime_T_LP5
{
U8 dramType, cbtMode, readDBI;
U8 DivMode;
U16 freq;
U8 readLat, writeLat;
U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
U8 tras;
U8 trp;
U8 trpab;
U8 trc;
U8 trfc;
U8 trfcpb;
U8 txp;
U8 trtp;
U8 trcd;
U8 twr;
U8 twtr;
U8 twtr_l;
U8 tpbr2pbr;
U8 tpbr2act;
U8 tr2mrw;
U8 tw2mrw;
U8 tmrr2mrw;
U8 tmrw;
U8 tmrd;
U8 tmrwckel;
U8 tpde;
U8 tpdx;
U8 tmrri;
U8 trrd;
U8 tfaw;
U8 tr2w_odt_off;
U8 tr2w_odt_on;
U16 txrefcnt;
U8 wckrdoff;
U8 wckwroff;
U8 tzqcs;
U8 xrtw2w_odt_off;
U8 xrtw2w_odt_on;
U8 xrtw2r_odt_off_otf_off;
U8 xrtw2r_odt_on_otf_off;
U8 xrtw2r_odt_off_otf_on;
U8 xrtw2r_odt_on_otf_on;
U8 xrtr2w_odt_on;
U8 xrtr2w_odt_off;
U8 xrtr2r_odt_off;
U8 xrtr2r_odt_on;
U8 xrtw2w_odt_off_wck;
U8 xrtw2w_odt_on_wck;
U8 xrtw2r_odt_off_wck;
U8 xrtw2r_odt_on_wck;
U8 xrtr2w_odt_off_wck;
U8 xrtr2w_odt_on_wck;
U8 xrtr2r_wck;
U8 tr2mrr;
U8 hwset_mr2_op;
U8 hwset_mr13_op;
U8 hwset_vrcg_op;
U8 vrcgdis_prdcnt;
U8 lp5_cmd1to2en;
U8 trtpd;
U8 twtpd;
U8 tmrr2w;
U8 ckeprd;
U8 ckelckcnt;
U8 tcsh_cscal;
U8 tcacsh;
U8 tcsh;
U8 trcd_derate;
U8 trc_derate;
U8 tras_derate;
U8 trpab_derate;
U8 trp_derate;
U8 trrd_derate;
U8 zqlat2;
//DRAMC_REG_SHU_AC_TIME_05T ===================================
U8 tras_05T;
U8 trp_05T;
U8 trpab_05T;
U8 trc_05T;
U8 trfc_05T;
U8 trfcpb_05T;
U8 txp_05T;
U8 trtp_05T;
U8 trcd_05T;
U8 twr_05T;
U8 twtr_05T;
U8 twtr_l_05T;
U8 tr2mrw_05T;
U8 tw2mrw_05T;
U8 tmrr2mrw_05T;
U8 tmrw_05T;
U8 tmrd_05T;
U8 tmrwckel_05T;
U8 tpde_05T;
U8 tpdx_05T;
U8 tmrri_05T;
U8 trrd_05T;
U8 tfaw_05T;
U8 tr2w_odt_off_05T;
U8 tr2w_odt_on_05T;
U8 wckrdoff_05T;
U8 wckwroff_05T;
U8 trtpd_05T;
U8 twtpd_05T;
U8 tpbr2pbr_05T;
U8 tpbr2act_05T;
U8 trcd_derate_05T;
U8 trc_derate_05T;
U8 tras_derate_05T;
U8 trpab_derate_05T;
U8 trp_derate_05T;
U8 trrd_derate_05T;
} ACTime_T_LP5;
//ACTimingTbl[] forward declaration
extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p);
extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p);
#endif

285
src/vendorcode/mediatek/mt8195/include/dramc_common.h Normal file
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@@ -0,0 +1,285 @@
/*
*
* DRAMC_COMMON.H
*
*/
#ifndef _DRAMC_COMMON_H_
#define _DRAMC_COMMON_H_
#include <soc/dramc_soc.h>
#include <delay.h>
#include <device/mmio.h>
#include <stdint.h>
#include <types.h>
#include <reg.h>
#include <soc/dramc_common.h>
#include <timer.h>
#include <print.h>
#include <string.h>
#include "dramc_register.h"
#include "dramc_pi_api.h"
#include "dramc_int_slt.h"
#include "print.h"
#include "reg.h"
#if FOR_DV_SIMULATION_USED == 1
#include "dramc_dv_init.h"
#else
#ifdef __DPM__
#include "dramc_dpm.h"
#elif __ETT__
#include "common.h"
#endif
#endif
#if __ETT__
#include "dramc_version.h"
#else
#define _VERSION_ "ETT Version 0.0.0.1"
#define _COMMIT_VERSION_ "01234567"
#define _COMMIT_DATE_ "2020-10-10/10:10:10"
#endif
/***********************************************************************/
/* Public Types */
/***********************************************************************/
/*------------------------------------------------------------*/
/* macros, defines, typedefs, enums */
/*------------------------------------------------------------*/
/************************** Common Macro *********************/
#define dsb() asm volatile("dsb sy" : : : "memory")
#define DRV_Reg32(x) read32((const void *)((u64)(x)))
#define DRV_WriteReg32(x, y) write32((void *)((u64)(x)), (y))
#define mcDELAY_US(x) udelay(x)
#define mcDELAY_MS(x) udelay(x*1000)
#define mcDELAY_XUS(x) udelay(x)
#define mcDELAY_XNS(x) udelay(1)
// choose a proper mcDELAY
#if defined(__DPM__)
#define mcDELAY_US(x) timer_busy_wait_us(TIMER3, x)
#define mcDELAY_XUS(x) timer_busy_wait_us(TIMER3, x)
#define mcDELAY_XNS(x) timer_busy_wait_us(TIMER3, 1)
#define mcDELAY_MS(x) timer_busy_wait_ms(TIMER3, x)
#endif
/**********************************************/
/* Priority of debug log */
/*--------------------------------------------*/
/* mcSHOW_DBG_MSG: High */
/* mcSHOW_DBG_MSG2: Medium High */
/* mcSHOW_DBG_MSG3: Medium Low */
/* mcSHOW_DBG_MSG4: Low */
/**********************************************/
#if __FLASH_TOOL_DA__
#define printf DBG_MSG
#define print DBG_MSG
#elif defined(RELEASE)
#if !__ETT__
#undef printf
#define printf
#undef print
#define print
#endif
#endif
#if FOR_DV_SIMULATION_USED
#define mcSHOW_DBG_MSG(_x_) {printf _x_;}
#define mcSHOW_DBG_MSG2(_x_) {printf _x_;}
#define mcSHOW_DBG_MSG3(_x_) {printf _x_;}
#define mcSHOW_DBG_MSG4(_x_) {printf _x_;}
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_) {printf _x_;}
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {printf _x_;}
#define mcSHOW_DUMP_INIT_RG_MSG(_x_) {printf _x_;}
#elif __ETT__
#if QT_GUI_Tool
#if MRW_CHECK_ONLY
#define mcSHOW_DBG_MSG_tmp(...) {printf (__VA_ARGS__); if(fp_A60868){fprintf (fp_A60868,__VA_ARGS__);}}
#define mcSHOW_DBG_MSG_Dump(...)
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_)
#define mcSHOW_DUMP_INIT_RG_MSG(_x_)
#define mcSHOW_MRW_MSG(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#else
#define mcSHOW_DBG_MSG_tmp(...) {printf (__VA_ARGS__); if(fp_A60868){fprintf (fp_A60868,__VA_ARGS__);}}
#define mcSHOW_DBG_MSG_Dump(...) {if(fp_A60868_RGDump){fprintf (fp_A60868_RGDump,__VA_ARGS__);}}
#define mcSHOW_DBG_MSG(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_DBG_MSG2(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_DBG_MSG3(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_DBG_MSG4(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_EYESCAN_MSG(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {mcSHOW_DBG_MSG_tmp _x_;}
#define mcSHOW_DUMP_INIT_RG_MSG(_x_)
#endif
#elif (defined(DDR_INIT_TIME_PROFILING))
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_) {opt_print _x_;}
#define mcSHOW_ERR_MSG(_x_)
#elif DUMP_ALLSUH_RG
#define mcSHOW_DBG_MSG(_x_) {mcDELAY_US(50);opt_print _x_;}
#define mcSHOW_DBG_MSG2(_x_) {mcDELAY_US(50); opt_print _x_;}
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {mcDELAY_US(50);opt_print _x_;}
#elif defined(RELEASE)
#define mcSHOW_DBG_MSG(_x_) //{opt_print _x_;}
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_) {opt_print _x_;}
#define mcSHOW_EYESCAN_MSG(_x_) {opt_print _x_;} //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {opt_print _x_;}
#elif VENDER_JV_LOG
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_) {opt_print _x_;} //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
#define mcSHOW_EYESCAN_MSG(_x_) {opt_print _x_;} //mcSHOW_JV_LOG_MSG(_x_) is for vendor JV
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_)
#elif SW_CHANGE_FOR_SIMULATION
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_)
#elif defined(DUMP_INIT_RG_LOG_TO_DE)
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_DUMP_INIT_RG_MSG(_x_) {gpt_busy_wait_us(50); print _x_;}
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_)
#elif MRW_CHECK_ONLY
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_MRW_MSG(_x_) {printf _x_;}
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_)
#else // ETT real chip
#define mcSHOW_DBG_MSG(_x_) {mcDELAY_US(10); print _x_;}
#define mcSHOW_DBG_MSG2(_x_) {mcDELAY_US(10); print _x_;}
#define mcSHOW_DBG_MSG3(_x_) {mcDELAY_US(10); print _x_;}
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_) {if (gEye_Scan_color_flag) {mcDELAY_US(200);}; print _x_;}
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {print _x_;}
#endif
#else // preloader
#if defined(DDR_INIT_TIME_PROFILING)
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_) {print _x_;}
#define mcSHOW_ERR_MSG(_x_)
#elif defined(TARGET_BUILD_VARIANT_ENG) //&& !defined(MTK_EFUSE_WRITER_SUPPORT) && !CFG_TEE_SUPPORT && !MTK_EMMC_SUPPORT
#define mcSHOW_DBG_MSG(_x_) {print _x_;}
#define mcSHOW_DBG_MSG2(_x_) {print _x_;}
#define mcSHOW_DBG_MSG3(_x_) {print _x_;}
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_) {print _x_;}
#if (CFG_DRAM_LOG_TO_STORAGE)
#define mcSHOW_EYESCAN_MSG(_x_) {print _x_;}
#define mcSHOW_JV_LOG_MSG(_x_) {print _x_;}
#else
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#endif
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {print _x_;}
#else
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_DBG_MSG3(_x_)
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_DBG_MSG6(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#define mcSHOW_EYESCAN_MSG(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcSHOW_ERR_MSG(_x_) {print _x_;}
#endif
#endif
#if QT_GUI_Tool ==1
#define mcFPRINTF(_x_) fprintf _x_;
#else
#define mcFPRINTF(_x_)
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0]))
#endif
#define enter_function() \
({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));})
#define exit_function() \
({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));})
extern int dump_log;
#endif // _DRAMC_COMMON_H_

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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to MediaTek Inc. and/or its licensors. Without
* the prior written permission of MediaTek inc. and/or its licensors, any
* reproduction, modification, use or disclosure of MediaTek Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
* SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
* RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
* MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("Media Tek
* Software") have been modified by MediaTek Inc. All revisions are subject to
* any receiver's applicable license agreements with MediaTek Inc.
*/
#ifndef __DRAMC_CUSTOM_H__
#define __DRAMC_CUSTOM_H__
//[FOR_CHROMEOS] Define the EMI_SETTINGS here
#include "dramc_top.h"
EMI_SETTINGS g_default_emi_setting = {
.type = 0x0006,
.EMI_CONA_VAL = 0xf053f154,
.EMI_CONF_VAL = 0x08421000,
.EMI_CONH_VAL = 0x44440083,
.EMI_CONK_VAL = 0x0,
.CHN0_EMI_CONA_VAL = 0x0400f051,
.CHN1_EMI_CONA_VAL = 0x0400f051,
.DRAM_RANK_SIZE = {0x100000000, 0x100000000, 0x0, 0x0},
.dram_cbt_mode_extern = CBT_R0_R1_BYTE,
.iLPDDR3_MODE_REG_5 = 0x6,
.highest_freq = 4266,
};
#endif /* __DRAMC_CUSTOM_H__ */

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#ifndef _DRAMC_DV_INIT_H_
#define _DRAMC_DV_INIT_H_
#include "dramc_common.h"
#include "dramc_int_global.h"
#include "x_hal_io.h"
#include "sv_c_data_traffic.h"
//=========================================================
//DRAM CONFIG ELEMENT COLLECTION
//=========================================================
typedef enum { DDR3, DDR4, LPDDR3, LPDDR4, LPDDR5, PSRAM } DRAM_TYPE_T;
typedef enum {BG4BK4, BK8, BK16, BKORG_RFU} e_BKORG;
typedef enum {DIS_both, EN_t, EN_both, EN_c} e_RDQSWCK;//MR20
#define SA_CONFIG_EN 1
#define DV_CONFIG_EN 1
//=========================================================
//Build Top configuration
//=========================================================
#define DFS_GROUP_NUM 10
#define CH_NUM 2
#define RK_NUM_PER_CH 2
#define DONT_CARE_VALUE 0
#define PULL_UP 1
#define PULL_DOWN 1
typedef struct Gating_config
{
U8 GAT_TRACK_EN ;
U8 RX_GATING_MODE ;
U8 RX_GATING_TRACK_MODE ;
U8 SELPH_MODE ;
U8 PICG_EARLY_EN ;
U8 VALID_LAT_VALUE ;
}Gating_confg_T;
//=========================================================
//DV configuration connection
//=========================================================
#if DV_CONFIG_EN==1
typedef struct DRAMC_DVFS_GROUP_transfer
{
U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1
U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes
U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode
U8 RESERVED_8BIT;
U32 data_rate ;
}DRAMC_DVFS_GROUP_transfer_T;
typedef struct DV_configuration
{
U8 EX_ROW_EN_1 ;
U8 EX_ROW_EN_0 ;
U8 BYTE_MODE_1 ;
U8 BYTE_MODE_0 ;
U8 LP4Y_EN ;
U8 LP4_WR_PST ;
U8 LP4_OTF ;
U8 NEW_8X_MODE ;
U8 LP45_APHY_COMB_EN;
U8 DLL_IDLE_MODE ;
U8 NEW_RANK_MODE ;
U8 DLL_ASYNC_EN ;
U8 MD32_EN ;
U8 SRAM_EN ;
U8 GP_NUM ;
} DV_new_config_T;
#endif
//=========================================================
//LPDDR4 DRAM config
//=========================================================
typedef struct LP4_DRAM_CONFIG
{
U8 BYTE_MODE[2]; //diff rank
U8 EX_ROW_EN[2]; //diff rank --density over 10G should 1
U8 MR_WL ;
U8 MR_RL ;
U8 BL ;
U8 RPST ;
U8 RD_PRE ;
U8 WR_PRE ;
U8 WR_PST ;
U8 DBI_WR ;
U8 DBI_RD ;
// U8 DMI ; //No use default enable
U8 OTF ;
U8 LP4Y_EN ;
U8 WORK_FSP ;
} LP4_DRAM_CONFIG_T;
//=========================================================
//LPDDR5 DRAM config
//=========================================================
typedef struct LP5_DRAM_CONFIG
{
U8 BYTE_MODE[2] ;
U8 EX_ROW_EN[2] ;
U8 MR_WL ;
U8 MR_RL ;
U8 BL ;
U8 CK_Mode ;
U8 RPST ;
U8 RD_PRE ;
U8 WR_PRE ;
U8 WR_PST ;
U8 DBI_WR ;
U8 DBI_RD ;
U8 DMI ;
U8 OTF ;
U8 WCK_PST ;
U8 RDQS_PRE ;
U8 RDQS_PST ;
U8 CA_ODT ;
U8 DQ_ODT ;
U8 CKR ;
U8 WCK_ON ;
U8 WCK_FM ;
U8 WCK_ODT ;
U8 DVFSQ ;
U8 DVFSC ;
e_RDQSWCK RDQSmode[2] ;
U8 WCKmode[2] ;
U8 RECC ;
U8 WECC ;
e_BKORG BankMode ;
U8 WORK_FSP ;
} LP5_DRAM_CONFIG_T;
//=========================================================
//Analog PHY config
//=========================================================
typedef struct ANA_top_function_config
{
U8 DLL_ASYNC_EN ;
U8 ALL_SLAVE_EN ;
U8 NEW_RANK_MODE ;
U8 DLL_IDLE_MODE ;
U8 LP45_APHY_COMB_EN;
U8 TX_ODT_DIS ;
U8 NEW_8X_MODE ;
U8 LP4_WDQS_MODE ;
}ANA_top_config_T;
typedef struct ANA_DVFS_core_config
{
U8 CKR;
U8 DQ_P2S_RATIO;
U8 LP5_1600_DQ_P2S_MODE;
U8 CA_P2S_RATIO;
U8 DQ_CA_OPEN;
U8 DQ_SEMI_OPEN;
U8 CA_SEMI_OPEN;
U8 CA_FULL_RATE;
U8 DQ_CKDIV4_EN;
U8 CA_CKDIV4_EN;
U8 CA_PREDIV_EN;
U8 PH8_DLY;
U8 SEMI_OPEN_CA_PICK_MCK_RATIO;
U8 DQ_AAMCK_DIV;
U8 CA_AAMCK_DIV;
U8 CA_ADMCK_DIV;
U8 DQ_TRACK_CA_EN;
U32 PLL_FREQ;
U8 DQ_UI_PI_RATIO;
U8 CA_UI_PI_RATIO;
} ANA_DVFS_CORE_T;
//=========================================================
//DVFS group configuration
//=========================================================
typedef struct DRAMC_DVFS_GROUP_CONFIG
{
U32 data_rate ;
U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes
U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode
U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1
}DRAMC_DVFS_GROUP_CONFIG_T;
//=========================================================
//DRAMC Subsystem config
//=========================================================
typedef struct DRAMC_SUBSYS_CONFIG
{
U8 GP_NUM ;
U8 SRAM_EN ;
U8 MD32_EN ;
ANA_top_config_T *a_cfg ;
ANA_DVFS_CORE_T *a_opt ;
LP4_DRAM_CONFIG_T *lp4_init ;
LP5_DRAM_CONFIG_T *lp5_init ;
DRAMC_DVFS_GROUP_CONFIG_T *DFS_GP[DFS_GROUP_NUM];
}DRAMC_SUBSYS_CONFIG_T;
typedef struct DUT_shuf_config_T {
U8 CKE_DBE_CNT ;
U8 FASTWAKE2 ;
U8 DMPGTIM ;
U8 ADVPREEN ;
U8 DLE_256EN ;
U8 LECC ;
U8 WPST1P5T_OPT ;
U8 LP4YEN ;
U8 LP5_CAS_MODE ;
U8 LP5_SEP_ACT ;
U8 LP5_BGOTF ;
U8 LP5_BGEN ;
U8 LP5_RDQS_SE_EN ;
U8 CKR ;
U8 DQSIEN_MODE ;
U8 DQ_P2S_RATIO ;
U32 data_rate ;
}__attribute__((packed)) DUT_shuf_config_T;
typedef struct DUT_top_set_T {
U8 PINMUX_setAB ;
U8 DVFSRTMRWEN ;
U8 NO_QUEUEFLUSH_EN ;
U8 RG_SPM_MODE ;
U8 MD32_EN ;
U8 SRAM_EN ;
U8 RX_PIPE_BYPASS_EN ;
U8 TX_PIPE_BYPASS_EN ;
U32 WAIT_DLE_EXT_DLY ;
U32 RX_DCM_EXT_DLY ;
U8 old_dcm_mode ;
U8 DPHY_DCM_MODE ;
U8 TX_OE_EXT_OPT ;
U8 TXP_WORKAROUND_OPT ;
U32 VALID_LAT_VALUE ;
U8 RXTRACK_PBYTE_OPT ;
U8 TRACK_UP_MODE ;
U8 TREFBWIG_IGNORE ;
U8 SELPH_MODE ;
U8 EX_ROW_EN_RK1 ;
U8 EX_ROW_EN_RK0 ;
U8 RANK_SWAP ;
U8 BGPIPE_EN ;
U8 PICG_MODE ;
U8 RTMRR_MODE ;
U8 TMRRI_MODE ;
U8 DQS_OSC_AT_TIMER ;
U8 WPST1P5T_OPT ;
U8 LP5_ZQ_OPT ;
U8 LP5WRAPEN ;
U8 LP4_SE_MODE ;
U8 LP4Y_EN ;
U8 LP4_WR_PST ;
U8 LP4_OTF ;
U8 PLL_MODE_OPTION ;
U8 NEW_8X_MODE ;
U8 LP45_APHY_COMB_EN ;
U8 DLL_IDLE_MODE ;
U8 NEW_RANK_MODE ;
U8 DLL_ASYNC_EN ;
U32 memory_type ;
U32 GP_NUM ;
}__attribute__((packed)) DUT_top_set_T;
extern Gating_confg_T Gat_p;
extern DRAM_TYPE_T MEM_TYPE;
extern LP4_DRAM_CONFIG_T LP4_INIT;
extern LP5_DRAM_CONFIG_T LP5_INIT;
extern ANA_top_config_T ana_top_p;
extern ANA_DVFS_CORE_T ANA_option;
extern DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
extern DRAMC_SUBSYS_CONFIG_T DV_p;
extern DRAMC_CTX_T *DramcConfig;
extern DUT_top_set_T DUTTopSetGlobal;
extern DUT_shuf_config_T DUTShufConfigGlobal[10];
#define A_T DV_p.a_cfg
#define A_D DV_p.a_opt
#define M_LP4 DV_p.lp4_init
#define DFS(i) DV_p.DFS_GP[i]
#define LPDDR5_EN_S ((MEM_TYPE==LPDDR5) ? 1 : 0)
#define LPDDR4_EN_S ((MEM_TYPE==LPDDR4) ? 1 : 0)
#define DUT_p DUTTopSetGlobal
#define DUT_shu_p DUTShufConfigGlobal
#if FOR_DV_SIMULATION_USED==1
EXTERN void register_write(int address, int data);
EXTERN void register_read(int address, int * data);
EXTERN void delay_us(u32 delta);
EXTERN void delay_ns(u32 delta);
EXTERN void timestamp_show();
EXTERN void build_api_initial();
EXTERN void register_write_c(u32 address, u32 data);
EXTERN u32 register_read_c(u32 address);
EXTERN void conf_to_sram_sudo(int ch_id , int group_id, int conf_id);
//================ added by Lingyun Wu 11.14 =====================
EXTERN void broadcast_on(void);
EXTERN void broadcast_off(void);
//================ added by Lingyun Wu 11.14 =====================
EXTERN void mygetscope();
EXTERN void mysetscope();
#endif
#if DV_CONFIG_EN
extern void get_dfs_configuration_from_DV_random(DRAMC_DVFS_GROUP_transfer_T * tr, int group_id);
extern void get_top_configuration_from_DV_random(DV_new_config_T * tr);
#endif
//DRAM LP4 initial configuration
extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr);
extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra);
extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr);
#if __LP5_COMBO__
extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr);
#endif
extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate);
extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs);
extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr);
extern void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id);
#endif // _DRAMC_DV_INIT_H_

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#ifndef _INT_GLOBAL_H
#define _INT_GLOBAL_H
#include "dramc_pi_api.h"
#include "dramc_int_slt.h"
/*
****************************************************************************************
** macro
****************************************************************************************
*/
#define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0
//#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING
//#define DVT_TEST_RX_DLY_HW_TRACKING
/*
****************************************************************************************
** ANA_init_config.c
****************************************************************************************
*/
EXTERN void ANA_init(DRAMC_CTX_T *p);
EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p);
/*
****************************************************************************************
** DIG_NONSHUF_config.c
****************************************************************************************
*/
EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p);
/*
****************************************************************************************
*
** DIG_SHUF_config.c
****************************************************************************************
*/
EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id);
/*
****************************************************************************************
*
** dramc_debug.c
****************************************************************************************
*/
EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX];
EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2];
EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX];
#ifdef FOR_HQA_REPORT_USED
EXTERN U8 gHQALog_flag;
EXTERN U16 gHQALOG_RX_delay_cell_ps_075V;
EXTERN U8 gHQALog_SLT_BIN[DRAM_DFS_SRAM_MAX];
#endif
// --- Eye scan variables -----
EXTERN U8 gCBT_EYE_Scan_flag;
EXTERN U8 gRX_EYE_Scan_flag;
EXTERN U8 gTX_EYE_Scan_flag;
EXTERN U8 gEye_Scan_color_flag;
EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gEye_Scan_unterm_highest_flag;
#if ENABLE_EYESCAN_GRAPH
#define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP)) //range0 0~50 + range1 21~50
#define EYESCAN_BROKEN_NUM 3
#define EYESCAN_DATA_INVALID 0x7f
EXTERN S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
EXTERN S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH][EYESCAN_BROKEN_NUM];
EXTERN S16 gEyeScan_MinMax_store_delay[DQS_BYTE_NUMBER];
EXTERN U16 gEyeScan_CaliDelay[DQS_BYTE_NUMBER];
EXTERN U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH];
EXTERN S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH];
EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH];
EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH];
EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p);
EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type);
#endif
#if MRW_CHECK_ONLY || MRW_BACKUP
EXTERN U8 gFSPWR_Flag[RANK_MAX];
#endif
#ifdef FOR_HQA_TEST_USED
EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p);
#endif
#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p);
#endif
#if DUMP_ALLSUH_RG
EXTERN void DumpAllChAllShuRG(DRAMC_CTX_T *p);
#endif
#if PIN_CHECK_TOOL
//EXTERN U8* print_Impedence_LOG_type(U8 print_type);
EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p);
EXTERN void vGetErrorTypeResult(DRAMC_CTX_T *p);
EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool;
#endif
#ifdef DEVIATION
extern U8 gSetSpecificedVref_Enable[];
extern U8 gSetSpecificedVref_Type;
extern U8 gSetSpecificedVref_All_ChRk[];
extern U8 gSetSpecificedVref_Channel[];
extern U8 gSetSpecificedVref_Rank[];
extern S8 gSetSpecificedVref_Vref_Offset[];
#endif
/*
****************************************************************************************
** dramc_dvfs.c
****************************************************************************************
*/
EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T SRAMIdx);
EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_SRAM_SHU_T dstRG);
EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG);
EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level);
EXTERN void DVFSSettings(DRAMC_CTX_T *p);
EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable);
EXTERN void DPMInit(DRAMC_CTX_T *p);
EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_dv_freq_related.c
****************************************************************************************
*/
EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p);
EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p);
EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_dv_main.c
****************************************************************************************
*/
#if (FOR_DV_SIMULATION_USED == 1)
EXTERN void DPI_DRAMC_init_entry();
EXTERN void DPI_DRAM_INIT();
#endif
/*
****************************************************************************************
** dramc_pi_basic.c
****************************************************************************************
*/
EXTERN U8 u1PrintModeRegWrite;
EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p);
EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p);
EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p);
//EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p);
//EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p);
#if CBT_MOVE_CA_INSTEAD_OF_CLK
EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value);
#endif
EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq);
EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround);
EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p);
EXTERN void Global_Option_Init(DRAMC_CTX_T *p);
EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p);
EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p);
EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p);
EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff);
EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p);
#if ENABLE_PER_BANK_REFRESH
EXTERN void DramcSetPerBankRefreshMode(DRAMC_CTX_T *p);
#endif
//EXTERN void RXPICGSetting(DRAMC_CTX_T * p);
EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p);
EXTERN unsigned int DDRPhyFreqMeter(DRAMC_CTX_T * p);
#ifndef DPM_CONTROL_AFTERK
EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p);
#endif
/*
****************************************************************************************
** dramc_pi_calibration_api.c
****************************************************************************************
*/
EXTERN U16 gu2MR0_Value[RANK_MAX]; //read only mode register
EXTERN U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX]; //ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN
EXTERN U8 gCBT_VREF_RANGE_SEL;
EXTERN JMETER_DELAYCELL_T JMeter_DelayCell_Table[DRAM_DFS_SRAM_MAX];
EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16];
EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16];
EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6];
EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6];
#if __ETT__
EXTERN U8 gETT_WHILE_1_flag;
#endif
#ifdef FOR_HQA_TEST_USED
EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10];
EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX];
EXTERN S8 gFinalClkDuty[CHANNEL_NUM];
EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2];
EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_BYTE_NUMBER];
EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_BYTE_NUMBER][2];
#endif
EXTERN U8 u1MR01Value[FSP_MAX];
EXTERN U8 u1MR02Value[FSP_MAX];
EXTERN U8 u1MR03Value[FSP_MAX];
EXTERN U8 u1MR11Value[FSP_MAX];
EXTERN U8 u1MR18Value[FSP_MAX];
EXTERN U8 u1MR19Value[FSP_MAX];
EXTERN U8 u1MR20Value[FSP_MAX];
EXTERN U8 u1MR21Value[FSP_MAX];
EXTERN U8 u1MR22Value[FSP_MAX];
EXTERN U8 u1MR51Value[FSP_MAX];
EXTERN U8 u1MR04Value[RANK_MAX];
EXTERN U8 u1MR13Value[RANK_MAX];
EXTERN U8 u1MR26Value[RANK_MAX];
EXTERN U8 u1MR30Value[RANK_MAX];
EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
#if PINMUX_AUTO_TEST_PER_BIT_RX
EXTERN U8 gRX_check_per_bit_flag;
EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
#endif
#if PINMUX_AUTO_TEST_PER_BIT_TX
EXTERN U8 gTX_check_per_bit_flag;
EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
#endif
EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK);
EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank);
EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type);
EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase);
EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs);
EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern, U8 *u1AssignedVref, U8 isAutoK, U8 K_Type);
EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region);
EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where);
EXTERN void vBeforeCalibration(DRAMC_CTX_T *p);
EXTERN void vAfterCalibration(DRAMC_CTX_T *p);
EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p);
EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p);
EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p);
//EXTERN void RODTSettings(DRAMC_CTX_T *p);
//EXTERN void DQSSTBSettings(DRAMC_CTX_T *p);
EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK);
EXTERN void DramPhyReset(DRAMC_CTX_T *p);
//EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p);
//EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p);
//EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p);
#if BYPASS_CALIBRATION
EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val);
EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]);
EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p);
EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p);
#endif
EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p);
EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p);
EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay);
EXTERN U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_pi_main.c
****************************************************************************************
*/
EXTERN DRAMC_CTX_T gTimeProfilingDramCtx;
EXTERN U8 gHQA_Test_Freq_Vcore_Level;
#if (FOR_DV_SIMULATION_USED == 1)
EXTERN U8 gu1BroadcastIsLP4;
#endif
EXTERN bool gAndroid_DVFS_en;
EXTERN bool gUpdateHighestFreq;
EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX];
EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p);
EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p);
EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p);
EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type);
#if __ETT__
EXTERN void ett_set_emi_rank1_address(void);
#endif
/*
****************************************************************************************
** dramc_slt.c
****************************************************************************************
*/
#if ENABLE_EMI_LPBK_TEST
EXTERN U8 gEmiLpbkTest;
#endif
EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA);
EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA);
EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p);
/*
****************************************************************************************
** dramc_temp_function.c
****************************************************************************************
*/
EXTERN DRAMC_CTX_T DramCtx_LPDDR4;
/*
****************************************************************************************
** dramc_tracking.c
****************************************************************************************
*/
EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p);
EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel);
#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p);
#endif
#if TDQSCK_PRECALCULATION_FOR_DVFS
EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p);
EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p);
#endif
EXTERN void DramcDQSOSCInit(void);
EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p);
#if ENABLE_TX_TRACKING
EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p);
EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p);
EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p);
#endif
#if RDSEL_TRACKING_EN
EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq);
EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p);
#endif
#ifdef HW_GATING
EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p);
#endif
#if ENABLE_PER_BANK_REFRESH
EXTERN void Enable_PerBank_Refresh(DRAMC_CTX_T *p);
#endif
EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p);
#ifdef IMPEDANCE_TRACKING_ENABLE
EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p);
#endif
EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p);
EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p);
EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_utility.c
****************************************************************************************
*/
EXTERN U16 gddrphyfmeter_value[DRAM_DFS_SRAM_MAX];
#if FOR_DV_SIMULATION_USED
EXTERN U8 u1BroadcastOnOff;
#endif
#if (fcFOR_CHIP_ID == fcA60868)
EXTERN U8 u1EnterRuntime;
#endif
EXTERN U8 u1MaType;
EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p);
EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode);
EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch);
EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable);
EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p);
EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p);
EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option);
EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank);
EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel);
EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p);
EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p);
EXTERN void lp5heff_restore(DRAMC_CTX_T *p);
EXTERN u8 is_lp5_family(DRAMC_CTX_T *p);
EXTERN U32 GetDramcBroadcast(void);
EXTERN void DramCLKAlwaysOnOff(DRAMC_CTX_T *p, U8 option, CHANNEL_RANK_SEL_T WriteChannelNUM);
EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option,
CHANNEL_RANK_SEL_T WriteChannelNUM);
EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num);
EXTERN U8 u1GetRank(DRAMC_CTX_T *p);
EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p);
EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p);
EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat);
EXTERN void DramcEngine2End(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift);
EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num);
EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p);
EXTERN u8 is_heff_mode(DRAMC_CTX_T *p);
EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift);
EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel);
EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type);
EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p);
EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p);
EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_SRAMIdx(DRAMC_CTX_T *p);
EXTERN void vSetChannelNumber(DRAMC_CTX_T *p);
EXTERN void vSetRankNumber(DRAMC_CTX_T *p);
EXTERN void vSetFSPNumber(DRAMC_CTX_T *p);
EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode);
EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p);
EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p);
EXTERN void DramcBroadcastOnOff(U32 bOnOff);
EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p);
EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode);
EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode);
EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue);
EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue);
EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value);
EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
#if MRW_CHECK_ONLY
EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p);
#endif
#if MRW_BACKUP
EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank);
#endif
#if QT_GUI_Tool
EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount);
EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p);
#endif
EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode);
EXTERN void vSet_Current_SRAMIdx(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex);
EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p);
EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
EXTERN void CheckDramcWBR(U32 u4address);
EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len);
#if PRINT_CALIBRATION_SUMMARY
EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p);
#endif
EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len);
EXTERN U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p);
#ifdef DDR_INIT_TIME_PROFILING
void TimeProfileGetTick(PROFILING_TIME_T *ptime);
U32 TimeProfileDiffUS(PROFILING_TIME_T *base);
void TimeProfileBegin(void);
UINT32 TimeProfileEnd(void);
#endif
/*
****************************************************************************************
** Hal_IO.cpp
****************************************************************************************
*/
#ifdef DUMP_INIT_RG_LOG_TO_DE
EXTERN U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag;
#endif
/*
****************************************************************************************
** dramc_utility.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p);
#endif
/*
****************************************************************************************
** dramc_debug.cpp
****************************************************************************************
*/
extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str);
extern void HQA_LOG_Print_Prefix_String(DRAMC_CTX_T *p);
extern void print_HQA_message_before_CalibrationAllChannel(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_utility_QT.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p);
EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p);
EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p);
EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p);
EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p);
EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p);
EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p);
EXTERN U32 DDRPhyFreqMeter(DRAMC_CTX_T * p);
#endif
/*
****************************************************************************************
** fake_engine.c
****************************************************************************************
*/
/*
****************************************************************************************
** low_power_test.c
****************************************************************************************
*/
EXTERN int global_which_test;
EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn);
EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p);
EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn);
EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p);
EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p);
#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff);
#endif
#define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh)
#define LOW_POWER_SCENARIO_S1 5
#define LOW_POWER_SCENARIO_S0 6
#define LOW_POWER_SCENARIO_PASR 7
#define LOW_POWER_SCENARIO_ALL 8
#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9
#define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10
#define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12
#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13
#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14
#define LOW_POWER_SCENARIO_PASR_1BANK 15
#define LOW_POWER_SCENARIO_PASR_2BANK 16
#define LOW_POWER_SCENARIO_PASR_4BANK 17
#define LOW_POWER_SCENARIO_PASR_8BANK 18
#define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19
#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21
#define AUTO_REFRESH_RESERVE_TEST 22
/*
****************************************************************************************
** low_power_test.c
****************************************************************************************
*/
EXTERN U8 u1StopMiniStress;
EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p);
/*
****************************************************************************************
** LP4_dram_init.c
****************************************************************************************
*/
EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank);
EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p);
EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p);
/*
****************************************************************************************
** LP5_dram_init.c
****************************************************************************************
*/
EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p);
EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p);
/*
****************************************************************************************
** system_init.c
****************************************************************************************
*/
#if (fcFOR_CHIP_ID == fcA60868)
EXTERN void syspll_init(DRAMC_CTX_T *p);
#endif
/*
****************************************************************************************
** dramc_utility_QT.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data);
EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data);
#endif
/*
****************************************************************************************
** svsim_dummy.c
****************************************************************************************
*/
#if (FOR_DV_SIMULATION_USED == 0)
#define delay_us(x)
#define delay_ns(x)
#define mysetscope()
#define broadcast_on()
#define broadcast_off()
#define timestamp_show()
#define build_api_initial()
#define conf_to_sram_sudo(...)
#endif
/*
****************************************************************************************
** RS232.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count);
EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count);
#endif
/*
****************************************************************************************
** ett_test.c
****************************************************************************************
*/
#ifdef DDR_INIT_TIME_PROFILING
extern U16 u2TimeProfileCnt;
#endif
extern int hqa_vmddr_voltage, hqa_vmddr_class;
#endif //_INT_GLOBAL_H

104
src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h Normal file
View File

@@ -0,0 +1,104 @@
#ifndef _INT_SLT_H
#define _INT_SLT_H
//======================== EMI LPBK TEST Definition =====================================
#if defined(SLT)
#define ENABLE_EMI_LPBK_TEST 1
#else
#define ENABLE_EMI_LPBK_TEST 0
#endif
#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used
#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO
#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window
#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode
#if ENABLE_EMI_LPBK_TEST
#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode)
#else
#define EMI_USE_TA2 0
#endif
/****************************
Summary:
1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode
8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode)
****************************/
#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R
#define EMI_LPBK_S1 0
#define FREQ_METER 1
#define DQSG_COUNTER 1
#define ADJUST_TXDLY_SCAN_RX_WIN 0
#define EMI_LPBK_K_TX 0
#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write
#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32
#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24
#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16
#define EMI_LPBK_USE_LP3_PINMUX 0
#define EMI_LPBK_8W1R 1
#if EMI_LPBK_1W1R
#undef EMI_LPBK_8W1R
#define EMI_LPBK_8W1R 0
#endif
#if EMI_LPBK_USE_THROUGH_IO
#define EMI_LPBK_USE_DDR_800 1
#else
#define EMI_LPBK_USE_DDR_800 0
#endif
//#define K_TX_DQS_DLY 0
#define LP4_4266_freq_meter 533 // //shu0 533
#define LP4_3733_freq_meter 464 // //shu0 464
#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386
#define LP4_2400_freq_meter 299 //shu6 299 shu5 299
#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191
#define LP4_1200_freq_meter 299 //shu2 299 shu1 299
#define LP4_800_freq_meter 199 //shu7 199
#if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0
/*
#define SLT
#undef ENABLE_TMRRI_NEW_MODE
#define ENABLE_TMRRI_NEW_MODE 0
#undef ENABLE_DUTY_SCAN_V2
#define ENABLE_DUTY_SCAN_V2 0
#undef ENABLE_RODT_TRACKING
#define ENABLE_RODT_TRACKING 0
#undef TX_K_DQM_WITH_WDBI
#define TX_K_DQM_WITH_WDBI 0
#undef ENABLE_WRITE_DBI
#define ENABLE_WRITE_DBI 0
*/
#if EMI_INT_LPBK_WL_DQS_RINGCNT
#undef EMI_LPBK_USE_THROUGH_IO
#define EMI_LPBK_USE_THROUGH_IO 1
#undef EMI_LPBK_USE_DDR_800
#define EMI_LPBK_USE_DDR_800 0
#endif
#endif
//#if (EMI_LPBK_DRAM_USED)
//#undef ENABLE_MIOCK_JMETER
//#define ENABLE_MIOCK_JMETER // for TX_PER_BIT_DELAY_CELL
//#endif
//=============================================================================
#endif //_INT_GLOBAL_H

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//
// REGISTER.H Register map include file
//
#ifndef _A60868_REGISTER_H_
#define _A60868_REGISTER_H_
#include "dramc_pi_api.h"
#define POS_BANK_NUM 16 // SW Virtual base address position
#if (fcFOR_CHIP_ID == fc8195)
#include "8195_Register_DDRPHY_MD32.h"
#include "8195_Register_DDRPHY_NAO.h"
#include "8195_Register_DDRPHY_AO.h"
#include "8195_Register_DRAMC_AO.h"
#include "8195_Register_DRAMC_NAO.h"
#else
#include "Register_DDRPHY_MD32.h"
#include "Register_DDRPHY_NAO.h"
#include "Register_DDRPHY_AO.h"
#include "Register_DRAMC_AO.h"
#include "Register_DRAMC_NAO.h"
#include "Register_SYSTEM.h"
#endif
#if FOR_DV_SIMULATION_USED
#define Channel_A_DRAMC_NAO_BASE_VIRTUAL 0x40000
#define Channel_B_DRAMC_NAO_BASE_VIRTUAL 0x50000
#define Channel_A_DRAMC_AO_BASE_VIRTUAL 0x60000
#define Channel_B_DRAMC_AO_BASE_VIRTUAL 0x70000
#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL 0x80000
#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL 0x90000
#define Channel_A_DDRPHY_AO_BASE_VIRTUAL 0xA0000
#define Channel_B_DDRPHY_AO_BASE_VIRTUAL 0xB0000
#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL 0xC0000
#define MAX_BASE_VIRTUAL 0xD0000
#else
// SW Virtual base address
#define Channel_A_DRAMC_NAO_BASE_VIRTUAL 0x40000
#define Channel_B_DRAMC_NAO_BASE_VIRTUAL 0x50000
#define Channel_C_DRAMC_NAO_BASE_VIRTUAL 0x60000
#define Channel_D_DRAMC_NAO_BASE_VIRTUAL 0x70000
#define Channel_A_DRAMC_AO_BASE_VIRTUAL 0x80000
#define Channel_B_DRAMC_AO_BASE_VIRTUAL 0x90000
#define Channel_C_DRAMC_AO_BASE_VIRTUAL 0xA0000
#define Channel_D_DRAMC_AO_BASE_VIRTUAL 0xB0000
#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL 0xC0000
#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL 0xD0000
#define Channel_C_DDRPHY_NAO_BASE_VIRTUAL 0xE0000
#define Channel_D_DDRPHY_NAO_BASE_VIRTUAL 0xF0000
#define Channel_A_DDRPHY_AO_BASE_VIRTUAL 0x100000
#define Channel_B_DDRPHY_AO_BASE_VIRTUAL 0x110000
#define Channel_C_DDRPHY_AO_BASE_VIRTUAL 0x120000
#define Channel_D_DDRPHY_AO_BASE_VIRTUAL 0x130000
#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL 0x140000
#define Channel_B_DDRPHY_DPM_BASE_VIRTUAL 0x150000
#define MAX_BASE_VIRTUAL 0x160000
#endif
#define DRAMC_WBR 0x100010B4
//#if (CHANNEL_NUM==4)
#define DRAMC_BROADCAST_ON_4CH 0x27f7f //4CH
//#else
#define DRAMC_BROADCAST_ON_2CH 0x7f //2CH
//#endif
#define DRAMC_BROADCAST_ON 0x1
#define DRAMC_BROADCAST_OFF 0x0
//Definitions indicating DRAMC, DDRPHY register shuffle offset
#define SHU_GRP_DRAMC_OFFSET 0x700
#define SHU_GRP_DDRPHY_OFFSET 0x700
#define DRAMC_REG_AO_SHU_OFFSET (0x700)
#define DRAMC_REG_AO_RANK_OFFSET (0x200)
#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500
#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
#define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
#define DRAMC_REG_AO_SHUFFLE0_END_ADDR (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8
#define DDRPHY_AO_B0_B1_OFFSET (0x180)
#define DDRPHY_AO_SHU_OFFSET (0x700)
#define DDRPHY_AO_RANK_OFFSET (0x80)
#define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060
#define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0
#define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360
#define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760
#define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0
#define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60
#define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0
#define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_SHUFFLE0_BASE_ADDR (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700
#define DDRPHY_AO_SHUFFLE0_END_ADDR (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4
#define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET (0x20)
#define DDRPHY_NAO_GATING_STATUS_RK_OFFSET (0x10)
#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600
#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640
#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680
#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_GATING_STATUS_START (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420
#define DDRPHY_NAO_RANK0_GATING_STATUS_END (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET)
#define DRAMC_REG_NAO_RANK_OFFSET (0x200)
#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900
#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET)
// HW Physical base address
#if defined(__DPM__)
/* MD32 address */
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x300A2000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x300B2000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x300A8000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x300B8000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x300A6000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x300B6000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x300AA000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x300BA000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x30040000
#elif (FOR_DV_SIMULATION_USED)
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x40000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x20000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x50000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x30000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x60000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x70000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x80000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim
#elif(HAPS_FPFG_A60868 ==0)
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x10250000
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x10260000
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x10254000
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x10264000
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x10258000
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x10268000
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x10256000
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x10266000
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000
#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x10A40000
#else // A60868 FPGA Base Address
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x40000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x70000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x80000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x100000
#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x0
#endif
#define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n"
#endif // _A60868_REGISTER_H_

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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to MediaTek Inc. and/or its licensors. Without
* the prior written permission of MediaTek inc. and/or its licensors, any
* reproduction, modification, use or disclosure of MediaTek Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
* SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
* RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
* MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("Media Tek
* Software") have been modified by MediaTek Inc. All revisions are subject to
* any receiver's applicable license agreements with MediaTek Inc.
*/
#ifndef __DRAMC_TOP_H__
#define __DRAMC_TOP_H__
#ifdef FLASH_TOOL_DA
#include "sw_types.h"
#else
#include "dramc_typedefs.h"
#endif
#include "dramc_common.h"
#if __ETT__
#if (FOR_DV_SIMULATION_USED==0)
#define DRAM_ADAPTIVE
#endif
#endif
#define DRAM_ADAPTIVE
#define DRAM_BASE 0x40000000ULL
#define DDR_BASE DRAM_BASE
#if __ETT__
#define dramc_crit printf
#define dramc_debug printf
#elif __FLASH_TOOL_DA__
#define dramc_crit LOGD
#define dramc_debug LOGD
#else
#define dramc_crit print
#define dramc_debug printf
#endif
#define DRAMC_MAX_CH 4
#define DRAMC_MAX_RK 2
#define DRAMC_MR_CNT 4
#define DRAMC_FREQ_CNT 7
struct mr_info_t {
u16 mr_index;
u16 mr_value;
};
//[FOR_CHROMEOS]
extern struct dramc_param *dramc_params;
enum DRAM_TYPE {
DTYPE_DDR1 = 1,
DTYPE_LPDDR2,
DTYPE_LPDDR3,
DTYPE_PCDDR3,
DTYPE_LPDDR4,
DTYPE_LPDDR4X,
DTYPE_LPDDR4P
};
int mt_get_dram_type(void);
int get_dram_channel_support_nr(void);
int get_dram_channel_nr(void);
int get_dram_rank_nr(void);
int get_dram_mr_cnt(void);
int get_dram_freq_cnt(void);
#if !__ETT__
void get_dram_rank_size(u64 dram_rank_size[]);
void get_dram_freq_step(u32 dram_freq_step[]);
void set_dram_mr(unsigned int index, unsigned short value);
unsigned short get_dram_mr(unsigned int index);
void get_dram_mr_info(struct mr_info_t mr_info[]);
void reserve_dramc_dummy_read(void);
#endif
typedef struct _AC_TIMING_EXTERNAL_T
{
// U 00
U32 AC_TIME_EMI_FREQUENCY :16;
U32 AC_TIME_EMI_TRAS :8;
U32 AC_TIME_EMI_TRP :8;
// U 01
U32 AC_TIME_EMI_TRPAB :8;
U32 AC_TIME_EMI_TRC :8;
U32 AC_TIME_EMI_TRFC :8;
U32 AC_TIME_EMI_TRFCPB :8;
// U 02
U32 AC_TIME_EMI_TXP :8;
U32 AC_TIME_EMI_TRTP :8;
U32 AC_TIME_EMI_TRCD :8;
U32 AC_TIME_EMI_TWR :8;
// U 03
U32 AC_TIME_EMI_TWTR :8;
U32 AC_TIME_EMI_TRRD :8;
U32 AC_TIME_EMI_TFAW :8;
U32 AC_TIME_EMI_TRTW_ODT_OFF :4;
U32 AC_TIME_EMI_TRTW_ODT_ON :4;
// U 04
U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0)
U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1)
U32 AC_TIME_EMI_TXREFCNT :8;
U32 AC_TIME_EMI_TZQCS :8;
// U 05
U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new
// U 06
// Byte0
U32 AC_TIME_EMI_TRAS_05T :2;
U32 AC_TIME_EMI_TRP_05T :2;
U32 AC_TIME_EMI_TRPAB_05T :2;
U32 AC_TIME_EMI_TRC_05T :2;
// Byte1
U32 AC_TIME_EMI_TRFC_05T :2;
U32 AC_TIME_EMI_TRFCPB_05T :2;
U32 AC_TIME_EMI_TXP_05T :2;
U32 AC_TIME_EMI_TRTP_05T :2;
// Byte2
U32 AC_TIME_EMI_TRCD_05T :2;
U32 AC_TIME_EMI_TWR_05T :2;
U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified
U32 AC_TIME_EMI_TRRD_05T :2;
// Byte3
U32 AC_TIME_EMI_TFAW_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2;
U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new
// U 07
// Byte0
U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
}AC_TIMING_EXTERNAL_T;
//[FOR_CHROMEOS] Move EMI_SETTINGS to dramc_custom.h
typedef struct {
unsigned int type; /* 0x0000 : Invalid
0x0001 : Discrete DDR1
0x0002 : Discrete LPDDR2
0x0003 : Discrete LPDDR3
0x0004 : Discrete PCDDR3
0x0005 : Discrete LPDDR4
0x0006 : Discrete LPDR4X
0x0101 : MCP(NAND+DDR1)
0x0102 : MCP(NAND+LPDDR2)
0x0103 : MCP(NAND+LPDDR3)
0x0104 : MCP(NAND+PCDDR3)
0x0201 : MCP(eMMC+DDR1)
0x0202 : MCP(eMMC+LPDDR2)
0x0203 : MCP(eMMC+LPDDR3)
0x0204 : MCP(eMMC+PCDDR3)
0x0205 : MCP(eMMC+LPDDR4)
0x0206 : MCP(eMMC+LPDR4X) */
unsigned int EMI_CONA_VAL;
unsigned int EMI_CONH_VAL;
unsigned int EMI_CONK_VAL;
unsigned int EMI_CONF_VAL;
unsigned int CHN0_EMI_CONA_VAL;
unsigned int CHN1_EMI_CONA_VAL;
u64 DRAM_RANK_SIZE[4];
unsigned int dram_cbt_mode_extern;
unsigned int iLPDDR3_MODE_REG_5;
unsigned int highest_freq;
} EMI_SETTINGS;
typedef struct {
unsigned int type;
unsigned int id_length; /* storage ID lengty */
unsigned char ID[16]; /* storage ID */
u64 DRAM_RANK_SIZE[4];
unsigned int reserved[6];
unsigned int iLPDDR3_MODE_REG_5;
} QVL_LIST_T;
//typedef EMI_SETTINGS_v15 EMI_SETTINGS;
#if (FOR_DV_SIMULATION_USED==0)
void setup_dramc_voltage_by_pmic(void);
void switch_dramc_voltage_to_auto_mode(void);
#if ! __ETT__
uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting.
#endif
#endif
extern int num_of_emi_records;
extern EMI_SETTINGS g_default_emi_setting;
extern unsigned int channel_num_auxadc;
#if DRAM_AUXADC_CONFIG
extern unsigned int dram_type_auxadc;
#endif
#include "x_hal_io.h"
void init_ta2_single_channel(unsigned int);
#ifdef LAST_DRAMC
#define LAST_DRAMC_MAGIC_PATTERN 0x19870611
static void update_last_dramc_info(void);
void init_ta2_all_channel(void);
typedef struct {
unsigned long long ta2_result_magic;
unsigned long long ta2_result_last;
unsigned long long ta2_result_past;
unsigned long long ta2_result_checksum;
unsigned long long reboot_count;
volatile unsigned int last_fatal_err_flag;
volatile unsigned int fatal_err_flag;
volatile unsigned int storage_api_err_flag;
volatile unsigned int last_gating_err[4][2]; // [channel][rank]
volatile unsigned int gating_err[4][2]; // [channel][rank]
unsigned short mr5;
unsigned short mr6;
unsigned short mr7;
unsigned short mr8;
} LAST_DRAMC_INFO_T;
#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T
#define OFFSET_DRAM_FATAL_ERR (31)
#define OFFSET_DRAM_TA2_ERR (23)
#define OFFSET_DRAM_GATING_ERR (7)
#define OFFSET_CPU_RW_ERR (5)
#define OFFSET_DDR_RSV_MODE_FLOW (4)
#define OFFSET_DDR_RSV_MODE_ERR (3)
#define OFFSET_EMI_DCS_ERR (2)
#define OFFSET_DVFSRC_ERR (1)
#define OFFSET_DRS_ERR (0)
#define ERR_DRAM_TA2_RK0 (1 << 0)
#define ERR_DRAM_TA2_RK1 (1 << 1)
#define ERR_DRAM_GATING_RK0_R (1 << 0)
#define ERR_DRAM_GATING_RK0_F (1 << 1)
#define ERR_DRAM_GATING_RK1_R (1 << 2)
#define ERR_DRAM_GATING_RK1_F (1 << 3)
#define ERR_CPU_RW_RK0 (1 << 0)
#define ERR_CPU_RW_RK1 (1 << 1)
/* 0x1f -> bit[4:0] is for DDR reserve mode */
#define DDR_RSV_MODE_ERR_MASK (0x1f)
unsigned int check_last_dram_fatal_exception(void);
unsigned int check_dram_fatal_exception(void);
void set_err_code_for_storage_api(void);
void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code);
void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code);
void dram_fatal_set_cpu_rw_err(unsigned int err_code);
void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code);
void dram_fatal_backup_stberr(void);
void dram_fatal_init_stberr(void);
void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
#if 0//DRAM_AUXADC_CONFIG
unsigned int get_ch_num_by_auxadc(void);
#endif
#define dram_fatal_set_cpu_rw_err(err_code)\
do {\
dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\
} while(0)
#define dram_fatal_set_ddr_rsv_mode_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\
} while(0)
#define dram_fatal_set_emi_dcs_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\
} while(0)
#define dram_fatal_set_dvfsrc_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\
} while(0)
#define dram_fatal_set_drs_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\
} while(0)
#define dram_fatal_set_ddr_rsv_mode_flow()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
} while(0)
#endif //LAST_DRAMC
typedef enum {
KSHU0 = 0,
KSHU1,
KSHU2,
KSHU3,
KSHU4,
KSHU5,
KSHU6,
KSHU7,
KSHU8,
KSHU9,
} DRAM_KSHU;
typedef enum {
TYPE_VDRAM = 0,
TYPE_VDDR1,
TYPE_VDDR2,
TYPE_VDDQ,
} TYPE_VOLTAGE;
typedef enum {
LEVEL_VB = 0,
LEVEL_HV,
LEVEL_NV,
LEVEL_LV,
} LEVEL_VOLTAGE;
//================================================
//=============pmic related api for ETT HQA test ==============
//================================================
#if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE)
#define DRAM_HQA
#endif
#define MAX_VCORE 1193750
#define MAX_VDRAM 1300000
#define MAX_VDDQ 1300000
#define MAX_VMDDR 2000000
#define MAX_VIO18 1900000
#define UNIT_VCORE 6250
#define UNIT_VDRAM 5000
#define UNIT_VDDQ 10000
#define UNIT_VMDDR 10000
#define UNIT_VIO18 10000
#define UNIT_VIO18_STEP 100000
#define HQA_VIO18_HV 1950000
#define HQA_VCORE_HV_LP4_KSHU0_PL 787500
#define HQA_VCORE_HV_LP4_KSHU1_PL 737500
#define HQA_VCORE_HV_LP4_KSHU2_PL 712500
#define HQA_VCORE_HV_LP4_KSHU3_PL 712500
#define HQA_VCORE_HV_LP4_KSHU4_PL 687500
#define HQA_VCORE_HV_LP4_KSHU5_PL 687500
#define HQA_VCORE_HV_LP4_KSHU6_PL 687500
#define HQA_VCORE_HV_LP4_KSHU0_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU1_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU2_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU3_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU4_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU5_ETT 787500
#define HQA_VCORE_HV_LP4_KSHU6_ETT 787500
#define HQA_VDRAM_HV_LP4 1170000
#define HQA_VDDQ_HV_LP4 650000
#define HQA_VMDDR_HV_LP4 790000
#if defined(MTK_AGING_FLAVOR_LOAD)
#define HQA_VIO18_NV 1730000
#else
#define HQA_VIO18_NV 1800000
#endif
#define HQA_VCORE_NV_LP4_KSHU0_PL 750000
#define HQA_VCORE_NV_LP4_KSHU1_PL 700000
#define HQA_VCORE_NV_LP4_KSHU2_PL 675000
#define HQA_VCORE_NV_LP4_KSHU3_PL 675000
#define HQA_VCORE_NV_LP4_KSHU4_PL 650000
#define HQA_VCORE_NV_LP4_KSHU5_PL 650000
#define HQA_VCORE_NV_LP4_KSHU6_PL 650000
#define HQA_VCORE_NV_LP4_KSHU0_ETT 750000
#define HQA_VCORE_NV_LP4_KSHU1_ETT 700000
#define HQA_VCORE_NV_LP4_KSHU2_ETT 675000
#define HQA_VCORE_NV_LP4_KSHU3_ETT 675000
#define HQA_VCORE_NV_LP4_KSHU4_ETT 650000
#define HQA_VCORE_NV_LP4_KSHU5_ETT 650000
#define HQA_VCORE_NV_LP4_KSHU6_ETT 650000
#if defined(MTK_AGING_FLAVOR_LOAD)
#define HQA_VDRAM_NV_LP4 1060000
#define HQA_VDDQ_NV_LP4 570000
#define HQA_VMDDR_NV_LP4 710000
#else
#define HQA_VDRAM_NV_LP4 1125000
#define HQA_VDDQ_NV_LP4 600000
#define HQA_VMDDR_NV_LP4 750000
#endif
#define HQA_VIO18_LV 1730000
#define HQA_VCORE_LV_LP4_KSHU0_PL 712500
#define HQA_VCORE_LV_LP4_KSHU1_PL 662500
#define HQA_VCORE_LV_LP4_KSHU2_PL 637500
#define HQA_VCORE_LV_LP4_KSHU3_PL 637500
#define HQA_VCORE_LV_LP4_KSHU4_PL 612500
#define HQA_VCORE_LV_LP4_KSHU5_PL 612500
#define HQA_VCORE_LV_LP4_KSHU6_PL 612500
#define HQA_VCORE_LV_LP4_KSHU0_ETT 712500
#define HQA_VCORE_LV_LP4_KSHU1_ETT 612500
#define HQA_VCORE_LV_LP4_KSHU2_ETT 568750
#define HQA_VCORE_LV_LP4_KSHU3_ETT 568750
#define HQA_VCORE_LV_LP4_KSHU4_ETT 518750
#define HQA_VCORE_LV_LP4_KSHU5_ETT 518750
#define HQA_VCORE_LV_LP4_KSHU6_ETT 518750
#define HQA_VDRAM_LV_LP4 1060000
#define HQA_VDDQ_LV_LP4 570000
#define HQA_VMDDR_LV_LP4 710000
#define _SEL_PREFIX_SHU_PL(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_PL
#define _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_ETT
#define _SEL_PREFIX(type,vol,dtype) HQA_##type##_##vol##_##dtype
#define _SEL_VIO18(vol) HQA_VIO18_##vol
#define STD_VIO18 _SEL_VIO18(NV)
#define STD_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
#define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype)
#define STD_VDDQ _SEL_PREFIX(VDDQ,NV,LP4)
#define STD_VMDDR _SEL_PREFIX(VMDDR,NV,LP4)
#if defined(MTK_AGING_FLAVOR_LOAD)
#define DRAM_HQA
#endif
#ifdef DRAM_HQA
//#define HVCORE_HVDRAM
#if defined(MTK_AGING_FLAVOR_LOAD)
#define LVCORE_LVDRAM
#else
#define NVCORE_NVDRAM
//#define LVCORE_LVDRAM
//#define HVCORE_HVDRAM
#endif
#if defined(HVCORE_HVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4)
#define HQA_VIO18 _SEL_VIO18(HV)
#elif defined(NVCORE_NVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,NV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,NV,LP4)
#define HQA_VIO18 _SEL_VIO18(NV)
#elif defined(LVCORE_LVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4)
#define HQA_VIO18 _SEL_VIO18(LV)
#elif defined(HVCORE_LVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4)
#define HQA_VIO18 _SEL_VIO18(LV)
#elif defined(LVCORE_HVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4)
#define HQA_VIO18 _SEL_VIO18(HV)
#else
#error "Please set HQA voltage type"
#endif
#define SEL_PREFIX_VCORE(dtype,shu) HQA_VCORE(dtype,shu)
#define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype)
#define SEL_PREFIX_VDDQ HQA_VDDQ
#define SEL_PREFIX_VMDDR HQA_VMDDR
#define SEL_VIO18 HQA_VIO18
#else
#if defined(MTK_AGING_FLAVOR_LOAD)
//#define VCORE_BIN
#endif
#if !__ETT__
//#define VCORE_BIN
#endif
#define SEL_PREFIX_VCORE(dtype,shu) STD_VCORE(dtype,shu)
#define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype)
#define SEL_PREFIX_VDDQ STD_VDDQ
#define SEL_PREFIX_VMDDR STD_VMDDR
#define SEL_VIO18 STD_VIO18
#endif // #define DRAM_HQA
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
#define PART_DRAM_DATA_SIZE 0x100000
#define DRAM_CALIBRATION_DATA_MAGIC 0x9502
typedef struct _DRAM_CALIBRATION_HEADER_T
{
u32 pl_version;
u16 magic_number;
u32 calib_err_code;
} DRAM_CALIBRATION_HEADER_T;
typedef struct _DRAM_CALIBRATION_MRR_DATA_T
{
u16 checksum;
u16 emi_checksum;
DRAM_INFO_BY_MRR_T DramInfo;
} DRAM_CALIBRATION_MRR_DATA_T;
typedef struct _DRAM_CALIBRATION_SHU_DATA_T
{
u16 checksum;
u32 calib_err_code;
SAVE_TIME_FOR_CALIBRATION_T calibration_data;
} DRAM_CALIBRATION_SHU_DATA_T;
typedef struct _DRAM_CALIBRATION_DATA_T
{
DRAM_CALIBRATION_HEADER_T header;
DRAM_CALIBRATION_MRR_DATA_T mrr_info;
DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SRAM_MAX];
} DRAM_CALIBRATION_DATA_T;
/*
* g_dram_storage_api_err_code:
* bit[0:3] -> read api
* bit[4:7] -> write api
* bit[8:11] -> clean api
* bit[12:12] -> data formatted due to fatal exception
*/
#define ERR_NULL_POINTER (0x1)
#define ERR_MAGIC_NUMBER (0x2)
#define ERR_CHECKSUM (0x3)
#define ERR_PL_UPDATED (0x4)
#define ERR_BLKDEV_NOT_FOUND (0x5)
#define ERR_BLKDEV_READ_FAIL (0x6)
#define ERR_BLKDEV_WRITE_FAIL (0x7)
#define ERR_BLKDEV_NO_PART (0x8)
#define ERR_DATA_FORMATTED_OFFSET (12)
typedef enum {
DRAM_STORAGE_API_READ = 0,
DRAM_STORAGE_API_WRITE,
DRAM_STORAGE_API_CLEAN,
} DRAM_STORAGE_API_TPYE;
extern u32 g_dram_storage_api_err_code;
#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \
do {\
g_dram_storage_api_err_code |= (err_type << (api_type * 4));\
} while(0)
#define SET_DATA_FORMATTED_STORAGE_API_ERR() \
do {\
g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\
} while(0)
int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
int write_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
int clean_dram_calibration_data(void);
void dram_fatal_exception_detection_start(void);
void dram_fatal_exception_detection_end(void);
#define CBT_VREF_OFFSET 2
#define WRITE_LEVELING_OFFSET 5
#define GATING_START_OFFSET 0
#define GATING_PASS_WIN_OFFSET 3
#define RX_WIN_PERBIT_OFFSET 5
#define RX_WIN_PERBIT_VREF_OFFSET 4
#define TX_WIN_PERBIT_OFFSET 5
#define TX_WIN_PERBIT_VREF_OFFSET 4
#define RX_DATLAT_OFFSET 1
#define RX_WIN_HIGH_SPEED_TH 10
#define RX_WIN_LOW_SPEED_TH 100
#define TX_WIN_TH 12
#endif
#if defined(SLT)
#define SLT_ERR_NO_DATA (-1)
#define SLT_ERR_NO_DEV (-2)
#define SLT_ERR_NO_ADDR (-3)
#define SLT_ERR_WRITE_FAIL (-4)
#define SLT_ERR_READ_FAIL (-5)
typedef struct _DRAM_SLT_HEADER_T
{
u32 pl_version;
int stage_status;
} DRAM_SLT_HEADER_T;
typedef struct _DRAM_SLT_DATA_T
{
DRAM_SLT_HEADER_T header;
u32 test_result[10];
} DRAM_SLT_DATA_T;
int read_slt_data(DRAM_SLT_DATA_T *data);
int write_slt_data(DRAM_SLT_DATA_T *data);
int clean_slt_data(void);
#endif
unsigned long long get_dram_size(void);
typedef struct {
unsigned long long full_sys_addr;
unsigned int addr;
unsigned int row;
unsigned int col;
unsigned char ch;
unsigned char rk;
unsigned char bk;
unsigned char dummy;
} dram_addr_t;
unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
unsigned int get_dummy_read_addr(dram_addr_t *dram_addr);
unsigned int is_discrete_lpddr4(void);
unsigned int DRAM_MRR(int MRR_num);
void dram_auto_detection(void);
int mt_get_freq_setting(DRAMC_CTX_T *p);
unsigned int dramc_get_vmdd_voltage(unsigned int ddr_type);
unsigned int dramc_get_vmddq_voltage(unsigned int ddr_type);
unsigned int dramc_set_vmdd_voltage(unsigned int ddr_type, unsigned int vdram);
unsigned int dramc_set_vmddq_voltage(unsigned int ddr_type, unsigned int vddq);
void release_dram(void);
#endif /* __DRAMC_TOP_H__ */

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#ifndef _DRAMC_TYPEDEFS_H_
#define _DRAMC_TYPEDEFS_H_
#include <stdint.h>
#define IMPORT EXTERN
#ifndef __cplusplus
#define EXTERN extern
#else
#define EXTERN extern "C"
#endif
#define LOCAL static
#define GLOBAL
#define EXPORT GLOBAL
#define EQ ==
#define NEQ !=
#define AND &&
#define OR ||
#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B)))
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#if 0
#ifndef NULL
#define NULL 0
#endif
#endif
#define ASSERT(expr) \
do{ if(!(expr)){while(1);} }while(0)
#if 0 //[FOR_CHROMEOS]
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
#ifndef BOOL
typedef unsigned char BOOL;
#endif
typedef unsigned long ulong;
typedef unsigned char uchar;
typedef unsigned int uint;
typedef signed char int8;
typedef signed short int16;
typedef signed long int32;
typedef signed int intx;
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned long uint32;
typedef unsigned int uintx;
typedef signed char S8;
typedef signed short S16;
typedef signed int S32;
typedef signed long long S64;
typedef unsigned char U8;
typedef unsigned short U16;
typedef unsigned int U32;
typedef unsigned long long U64;
typedef unsigned char US8;
typedef unsigned short US16;
typedef unsigned int US32;
typedef unsigned long long US64;
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
typedef unsigned char UINT8;
typedef unsigned short UINT16;
typedef unsigned int UINT32;
typedef unsigned short USHORT;
typedef signed char INT8;
typedef signed short INT16;
typedef signed int INT32;
typedef volatile signed char *P_S8;
typedef volatile signed short *P_S16;
typedef volatile signed int *P_S32;
typedef long LONG;
typedef unsigned char UBYTE;
typedef short SHORT;
typedef unsigned int *UINT32P;
typedef volatile unsigned short *UINT16P;
typedef volatile unsigned char *UINT8P;
typedef unsigned char *U8P;
typedef volatile unsigned char *P_U8;
typedef volatile unsigned short *P_U16;
typedef volatile unsigned int *P_U32;
typedef unsigned long long *P_U64;
typedef signed long long *P_S64;
typedef unsigned int uint;
typedef void VOID;
typedef unsigned char BYTE;
typedef float FLOAT;
#endif

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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to MediaTek Inc. and/or its licensors. Without
* the prior written permission of MediaTek inc. and/or its licensors, any
* reproduction, modification, use or disclosure of MediaTek Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
* SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
* RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
* MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("Media Tek
* Software") have been modified by MediaTek Inc. All revisions are subject to
* any receiver's applicable license agreements with MediaTek Inc.
*/
#ifndef __EMI_H__
#define __EMI_H__
#include <dramc_top.h>
#if __ETT__
#define emi_log printf
#elif __FLASH_TOOL_DA__
#define emi_log LOGD
#else
#define emi_log print
#endif
struct isu_info_t {
unsigned int buf_size;
unsigned long long buf_addr;
unsigned long long ver_addr;
unsigned long long con_addr;
};
#define EMI_ISU_BUF_SIZE 0x800000
#define LAST_EMI_MAGIC_PATTERN 0x19870611
typedef struct {
unsigned int isu_magic;
unsigned int isu_ctrl;
unsigned int isu_dram_type;
unsigned int isu_diff_us;
unsigned int isu_buf_l;
unsigned int isu_buf_h;
unsigned int isu_version;
unsigned int snst_last;
unsigned int snst_past;
unsigned int os_flag_sspm;
unsigned int os_flag_ap;
} LAST_EMI_INFO_T;
#define DEF_LAST_EMI LAST_EMI_INFO_T
typedef struct {
unsigned int dram_type;
unsigned int ch_num;
unsigned int rk_num;
unsigned int bank_width[DRAMC_MAX_RK];
unsigned int row_width[DRAMC_MAX_RK];
unsigned int col_width[DRAMC_MAX_RK];
U64 rank_size[DRAMC_MAX_RK];
} EMI_INFO_T;
void emi_init(void);
void emi_init2(void);
void clr_emi_mpu_prot(void);
void dis_emi_apb_prot(void);
int get_row_width_by_emi(unsigned int rank);
int get_channel_nr_by_emi(void);
int get_rank_nr_by_emi(void);
void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]);
void set_cen_emi_cona(unsigned int cona_val);
void set_cen_emi_conf(unsigned int conf_val);
void set_cen_emi_conh(unsigned int conh_val);
void set_chn_emi_cona(unsigned int cona_val);
void set_chn_emi_conc(unsigned int conc_val);
unsigned int get_cen_emi_cona(void);
unsigned int get_chn_emi_cona(void);
void enable_infra_emi_broadcast(unsigned int enable);
void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr);
unsigned int set_emi_before_rank1_mem_test(void);
void restore_emi_after_rank1_mem_test(void);
void get_emi_isu_info(struct isu_info_t *isu_info_ptr);
void reserve_emi_isu_buf(void);
void reserve_emi_mbist_buf(void);
void record_emi_snst(void);
unsigned long long platform_memory_size(void);
int update_emi_setting(EMI_SETTINGS *default_emi_setting, EMI_INFO_T *emi_info);
//int mt_mem_init();
#endif /* __EMI_H__ */

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#ifndef __EMI_HW_H__
#define __EMI_HW_H__
/* from EMI golden setting */
//#define EMI_MP_SETTING
#define REAL_CHIP_EMI_GOLDEN_SETTING
#define INFRA_DRAMC_REG_CONFIG (0x100010b4)
#define INFRACFG_AO_MEM_BASE (0x10002000)
#define SUB_INFRACFG_AO_MEM_BASE (0x1030E000)
#define MCUSYS_PAR_WRAP_BASE (0x0C530000)
#define EMI_BASE (0x10219000)
#define SUB_EMI_BASE (0x1021D000)
#define EMI_MPU_BASE (0x10226000)
#define SUB_EMI_MPU_BASE (0x10225000)
#define CHN0_EMI_BASE (0x10235000)
#define CHN1_EMI_BASE (0x10245000)
#define EMI_CONA (EMI_BASE+0x000)
#define EMI_CONB (EMI_BASE+0x008)
#define EMI_CONC (EMI_BASE+0x010)
#define EMI_COND (EMI_BASE+0x018)
#define EMI_CONE (EMI_BASE+0x020)
#define EMI_CONF (EMI_BASE+0x028)
#define EMI_CONG (EMI_BASE+0x030)
#define EMI_CONH (EMI_BASE+0x038)
#define EMI_CONH_2ND (EMI_BASE+0x03C)
#define EMI_CONI (EMI_BASE+0x040)
#define EMI_CONJ (EMI_BASE+0x048)
#define EMI_CONK (EMI_BASE+0x050)
#define EMI_CONM (EMI_BASE+0x060)
#define EMI_CONN (EMI_BASE+0x068)
#define EMI_CONO (EMI_BASE+0x070)
#define EMI_MDCT (EMI_BASE+0x078)
#define EMI_MDCT_2ND (EMI_BASE+0x07C)
#define EMI_IOCL (EMI_BASE+0x0D0)
#define EMI_IOCL_2ND (EMI_BASE+0x0D4)
#define EMI_IOCM (EMI_BASE+0x0D8)
#define EMI_IOCM_2ND (EMI_BASE+0x0DC)
#define EMI_TESTB (EMI_BASE+0x0E8)
#define EMI_TESTC (EMI_BASE+0x0F0)
#define EMI_TESTD (EMI_BASE+0x0F8)
#define EMI_ARBA (EMI_BASE+0x100)
#define EMI_ARBB (EMI_BASE+0x108)
#define EMI_ARBC (EMI_BASE+0x110)
#define EMI_ARBD (EMI_BASE+0x118)
#define EMI_ARBE (EMI_BASE+0x120)
#define EMI_ARBF (EMI_BASE+0x128)
#define EMI_ARBG (EMI_BASE+0x130)
#define EMI_ARBH (EMI_BASE+0x138)
#define EMI_ARBI (EMI_BASE+0x140)
#define EMI_ARBI_2ND (EMI_BASE+0x144)
#define EMI_ARBJ_2ND (EMI_BASE+0x14C)
#define EMI_ARBK (EMI_BASE+0x150)
#define EMI_ARBK_2ND (EMI_BASE+0x154)
#define EMI_SLCT (EMI_BASE+0x158)
#define EMI_MPUD0_ST (EMI_BASE+0x160)
#define EMI_MPUD1_ST (EMI_BASE+0x164)
#define EMI_MPUD2_ST (EMI_BASE+0x168)
#define EMI_MPUD3_ST (EMI_BASE+0x16C)
#define EMI_MPUD4_ST (EMI_BASE+0x170)
#define EMI_MPUD5_ST (EMI_BASE+0x174)
#define EMI_MPUD6_ST (EMI_BASE+0x178)
#define EMI_MPUD7_ST (EMI_BASE+0x17C)
#define EMI_MPUD8_ST (EMI_BASE+0x180)
#define EMI_MPUD9_ST (EMI_BASE+0x184)
#define EMI_MPUD10_ST (EMI_BASE+0x188)
#define EMI_MPUD11_ST (EMI_BASE+0x18C)
#define EMI_MPUD12_ST (EMI_BASE+0x190)
#define EMI_MPUD13_ST (EMI_BASE+0x194)
#define EMI_MPUD14_ST (EMI_BASE+0x198)
#define EMI_MPUD15_ST (EMI_BASE+0x19C)
#define EMI_MPUD16_ST (EMI_BASE+0x1A0)
#define EMI_MPUD17_ST (EMI_BASE+0x1A4)
#define EMI_MPUD18_ST (EMI_BASE+0x1A8)
#define EMI_MPUD19_ST (EMI_BASE+0x1AC)
#define EMI_MPUD20_ST (EMI_BASE+0x1B0)
#define EMI_MPUD21_ST (EMI_BASE+0x1B4)
#define EMI_MPUD22_ST (EMI_BASE+0x1B8)
#define EMI_MPUD23_ST (EMI_BASE+0x1BC)
#define EMI_MPUD24_ST (EMI_BASE+0x1C0)
#define EMI_MPUD25_ST (EMI_BASE+0x1C4)
#define EMI_MPUD26_ST (EMI_BASE+0x1C8)
#define EMI_MPUD27_ST (EMI_BASE+0x1CC)
#define EMI_MPUD28_ST (EMI_BASE+0x1D0)
#define EMI_MPUD29_ST (EMI_BASE+0x1D4)
#define EMI_MPUD30_ST (EMI_BASE+0x1D8)
#define EMI_MPUD31_ST (EMI_BASE+0x1DC)
#define EMI_MPUS (EMI_BASE+0x1F0)
#define EMI_MPUT (EMI_BASE+0x1F8)
#define EMI_MPUT_2ND (EMI_BASE+0x1FC)
#define EMI_D0_ST2 (EMI_BASE+0x200)
#define EMI_D1_ST2 (EMI_BASE+0x204)
#define EMI_D2_ST2 (EMI_BASE+0x208)
#define EMI_D3_ST2 (EMI_BASE+0x20C)
#define EMI_D4_ST2 (EMI_BASE+0x210)
#define EMI_D5_ST2 (EMI_BASE+0x214)
#define EMI_D6_ST2 (EMI_BASE+0x218)
#define EMI_D7_ST2 (EMI_BASE+0x21C)
#define EMI_D8_ST2 (EMI_BASE+0x220)
#define EMI_D9_ST2 (EMI_BASE+0x224)
#define EMI_D10_ST2 (EMI_BASE+0x228)
#define EMI_D11_ST2 (EMI_BASE+0x22C)
#define EMI_D12_ST2 (EMI_BASE+0x230)
#define EMI_D13_ST2 (EMI_BASE+0x234)
#define EMI_D14_ST2 (EMI_BASE+0x238)
#define EMI_D15_ST2 (EMI_BASE+0x23C)
#define EMI_D16_ST2 (EMI_BASE+0x240)
#define EMI_D17_ST2 (EMI_BASE+0x244)
#define EMI_D18_ST2 (EMI_BASE+0x248)
#define EMI_D19_ST2 (EMI_BASE+0x24C)
#define EMI_D20_ST2 (EMI_BASE+0x250)
#define EMI_D21_ST2 (EMI_BASE+0x254)
#define EMI_D22_ST2 (EMI_BASE+0x258)
#define EMI_D23_ST2 (EMI_BASE+0x25C)
#define EMI_D24_ST2 (EMI_BASE+0x260)
#define EMI_D25_ST2 (EMI_BASE+0x264)
#define EMI_D26_ST2 (EMI_BASE+0x268)
#define EMI_D27_ST2 (EMI_BASE+0x26C)
#define EMI_D28_ST2 (EMI_BASE+0x270)
#define EMI_D29_ST2 (EMI_BASE+0x274)
#define EMI_D30_ST2 (EMI_BASE+0x278)
#define EMI_D31_ST2 (EMI_BASE+0x27C)
#define EMI_BMEN (EMI_BASE+0x400)
#define EMI_BSTP (EMI_BASE+0x404)
#define EMI_BCNT (EMI_BASE+0x408)
#define EMI_TACT (EMI_BASE+0x410)
#define EMI_TSCT (EMI_BASE+0x418)
#define EMI_WACT (EMI_BASE+0x420)
#define EMI_WSCT (EMI_BASE+0x428)
#define EMI_BACT (EMI_BASE+0x430)
#define EMI_BSCT (EMI_BASE+0x438)
#define EMI_MSEL (EMI_BASE+0x440)
#define EMI_TSCT2 (EMI_BASE+0x448)
#define EMI_TSCT3 (EMI_BASE+0x450)
#define EMI_WSCT2 (EMI_BASE+0x458)
#define EMI_WSCT3 (EMI_BASE+0x460)
#define EMI_WSCT4 (EMI_BASE+0x464)
#define EMI_MSEL2 (EMI_BASE+0x468)
#define EMI_MSEL3 (EMI_BASE+0x470)
#define EMI_MSEL4 (EMI_BASE+0x478)
#define EMI_MSEL5 (EMI_BASE+0x480)
#define EMI_MSEL6 (EMI_BASE+0x488)
#define EMI_MSEL7 (EMI_BASE+0x490)
#define EMI_MSEL8 (EMI_BASE+0x498)
#define EMI_MSEL9 (EMI_BASE+0x4A0)
#define EMI_MSEL10 (EMI_BASE+0x4A8)
#define EMI_BMID0 (EMI_BASE+0x4B0)
#define EMI_BMID1 (EMI_BASE+0x4B4)
#define EMI_BMID2 (EMI_BASE+0x4B8)
#define EMI_BMID3 (EMI_BASE+0x4BC)
#define EMI_BMID4 (EMI_BASE+0x4C0)
#define EMI_BMID5 (EMI_BASE+0x4C4)
#define EMI_BMID6 (EMI_BASE+0x4C8)
#define EMI_BMID7 (EMI_BASE+0x4CC)
#define EMI_BMID8 (EMI_BASE+0x4D0)
#define EMI_BMID9 (EMI_BASE+0x4D4)
#define EMI_BMID10 (EMI_BASE+0x4D8)
#define EMI_BMEN1 (EMI_BASE+0x4E0)
#define EMI_BMEN2 (EMI_BASE+0x4E8)
#define EMI_BMRW0 (EMI_BASE+0x4F8)
#define EMI_BMRW1 (EMI_BASE+0x4FC)
#define EMI_TTYPE1 (EMI_BASE+0x500)
#define EMI_TTYPE2 (EMI_BASE+0x508)
#define EMI_TTYPE3 (EMI_BASE+0x510)
#define EMI_TTYPE4 (EMI_BASE+0x518)
#define EMI_TTYPE5 (EMI_BASE+0x520)
#define EMI_TTYPE6 (EMI_BASE+0x528)
#define EMI_TTYPE7 (EMI_BASE+0x530)
#define EMI_TTYPE8 (EMI_BASE+0x538)
#define EMI_TTYPE9 (EMI_BASE+0x540)
#define EMI_TTYPE10 (EMI_BASE+0x548)
#define EMI_TTYPE11 (EMI_BASE+0x550)
#define EMI_TTYPE12 (EMI_BASE+0x558)
#define EMI_TTYPE13 (EMI_BASE+0x560)
#define EMI_TTYPE14 (EMI_BASE+0x568)
#define EMI_TTYPE15 (EMI_BASE+0x570)
#define EMI_TTYPE16 (EMI_BASE+0x578)
#define EMI_TTYPE17 (EMI_BASE+0x580)
#define EMI_TTYPE18 (EMI_BASE+0x588)
#define EMI_TTYPE19 (EMI_BASE+0x590)
#define EMI_TTYPE20 (EMI_BASE+0x598)
#define EMI_TTYPE21 (EMI_BASE+0x5A0)
#define EMI_BWCT0 (EMI_BASE+0x5B0)
#define EMI_BWCT1 (EMI_BASE+0x5B4)
#define EMI_BWCT2 (EMI_BASE+0x5B8)
#define EMI_BWCT3 (EMI_BASE+0x5BC)
#define EMI_BWCT4 (EMI_BASE+0x5C0)
#define EMI_BWST0 (EMI_BASE+0x5C4)
#define EMI_BWST1 (EMI_BASE+0x5C8)
#define EMI_EX_CON (EMI_BASE+0x5D0)
#define EMI_EX_ST0 (EMI_BASE+0x5D4)
#define EMI_EX_ST1 (EMI_BASE+0x5D8)
#define EMI_EX_ST2 (EMI_BASE+0x5DC)
#define EMI_WP_ADR (EMI_BASE+0x5E0)
#define EMI_WP_ADR_2ND (EMI_BASE+0x5E4)
#define EMI_WP_CTRL (EMI_BASE+0x5E8)
#define EMI_CHKER (EMI_BASE+0x5F0)
#define EMI_CHKER_TYPE (EMI_BASE+0x5F4)
#define EMI_CHKER_ADR (EMI_BASE+0x5F8)
#define EMI_CHKER_ADR_2ND (EMI_BASE+0x5FC)
#define EMI_BWCT0_2ND (EMI_BASE+0x6A0)
#define EMI_LTCT0_2ND (EMI_BASE+0x750)
#define EMI_LTCT1_2ND (EMI_BASE+0x754)
#define EMI_LTCT2_2ND (EMI_BASE+0x758)
#define EMI_LTCT3_2ND (EMI_BASE+0x75C)
#define EMI_BWCT0_3RD (EMI_BASE+0x770)
#define EMI_BWCT0_4TH (EMI_BASE+0x780)
#define EMI_BWCT0_5TH (EMI_BASE+0x7B0)
#define EMI_BWCT0_6TH (EMI_BASE+0x7C8)
#define EMI_SNST (EMI_BASE+0x7F8)
#define EMI_SLVA (EMI_BASE+0x800)
#define EMI_AXI_BIST_ADR0 (EMI_BASE+0x98c)
#define EMI_AXI_BIST_ADR1 (EMI_BASE+0x990)
#define EMI_AXI_BIST_ADR2 (EMI_BASE+0x994)
#define EMI_MPU_CTRL (EMI_MPU_BASE+0x000)
#define EMI_MPU_DBG (EMI_MPU_BASE+0x004)
#define EMI_MPU_SA0 (EMI_MPU_BASE+0x100)
#define EMI_MPU_EA0 (EMI_MPU_BASE+0x200)
#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4))
#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4))
#define EMI_MPU_APC0 (EMI_MPU_BASE+0x300)
#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800)
#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4))
#define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900)
#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4))
#define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE+0x000)
#define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE+0x004)
#define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE+0x100)
#define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE+0x200)
#define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region*4))
#define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region*4))
#define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE+0x300)
#define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
#define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE+0x800)
#define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain*4))
#define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE+0x900)
#define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain*4))
#define CHN_EMI_CONA(base) (base + 0x000)
#define CHN_EMI_CONC(base) (base + 0x010)
#endif // __EMI_HW_H__

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#ifndef __EMI_MPU_MT_H__
#define __EMI_MPU_MT_H__
#define ENABLE_MPU 1
#define EMI_MPU_ALIGN_BITS 16
#define EMI_MPU_DOMAIN_NUM 16
#define EMI_MPU_REGION_NUM 32
#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
#define SSPM_MPU_REGION_ID 4
#endif /* __EMI_MPU_MT_H__ */

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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2011. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
fix* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef MT8195_H
#define MT8195_H
/*=======================================================================*/
/* Constant Definitions */
/*=======================================================================*/
#define IO_PHYS (0x10000000)
#define IO_SIZE (0x02000000)
#define VER_BASE (0x08000000)
/*=======================================================================*/
/* Register Bases */
/*=======================================================================*/
#define MCUCFG_BASE (0x0C530000)
#define TOPCKGEN_BASE (IO_PHYS)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define APMIXED_BASE (IO_PHYS + 0x0000C000)
#define INFRA_AO_BCRM_BASE (IO_PHYS + 0x00022000)
#define AUDIO_BASE (IO_PHYS + 0x00890000)
#define AUDIO_SRC_BASE (IO_PHYS + 0x008a0000)
#define CAMSYS_YUVB_BASE (IO_PHYS + 0x060af000)
#define CAMSYS_MAIN_BASE (IO_PHYS + 0x06000000)
#define CAMSYS_MRAW_BASE (IO_PHYS + 0x06140000)
#define CAMSYS_RAWA_BASE (IO_PHYS + 0x0604f000)
#define CAMSYS_RAWB_BASE (IO_PHYS + 0x0608f000)
#define CAMSYS_YUVA_BASE (IO_PHYS + 0x0606f000)
#define CCU_MAIN_BASE (IO_PHYS + 0x07200000)
#define IMGSYS1_DIP_NR_BASE (IO_PHYS + 0x05130000)
#define IMGSYS1_DIP_TOP_BASE (IO_PHYS + 0x05110000)
#define IMGSYS1_WPE_BASE (IO_PHYS + 0x05220000)
#define IMGSYS_MAIN_BASE (IO_PHYS + 0x05000000)
#define IPESYS_BASE (IO_PHYS + 0x05330000)
#define MFGCFG_BASE (IO_PHYS + 0x03fbf000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define SCP_PAR_TOP_BASE (IO_PHYS + 0x00720000)
#define IPNNA_BASE (IO_PHYS + 0x00211000)
#define VDEC_CORE1_GCON_BASE (IO_PHYS + 0x0803f000)
#define VDEC_GCON_BASE (IO_PHYS + 0x0802f000)
#define VDEC_SOC_GCON_BASE (IO_PHYS + 0x0800f000)
#define VDOSYS0_CONFIG_BASE (IO_PHYS + 0x0c01a000)
#define VDOSYS1_CONFIG_BASE (IO_PHYS + 0x0c100000)
#define VENC_CORE1_GCON_BASE (IO_PHYS + 0x0b000000)
#define VENC_GCON_BASE (IO_PHYS + 0x0a000000)
#define VPP0_REG_BASE (IO_PHYS + 0x04000000)
#define VPPSYS1_CONFIG_BASE (IO_PHYS + 0x04f00000)
#define WPESYS_TOP_REG_BASE (IO_PHYS + 0x04e00000)
#define WPE_VPP0_BASE (IO_PHYS + 0x04e02000)
#define WPE_VPP1_BASE (IO_PHYS + 0x04e03000)
#define IOCFG_BM_BASE (0x11D10000)
#define IOCFG_BL_BASE (0x11D30000)
#define IOCFG_BR_BASE (0x11D40000)
#define IOCFG_LM_BASE (0x11E20000)
#define IOCFG_RB_BASE (0x11EB0000)
#define IOCFG_TL_BASE (0x11F40000)
/*should be removed*/
#define PERICFG_BASE (IO_PHYS + 0x00003000)
//#define PERI_CON_BASE (IO_PHYS + 0x00003000)
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define RGU_BASE (IO_PHYS + 0x00007000)
#define GPT_BASE (IO_PHYS + 0x00008000)
#define SYSTIMER_BASE (IO_PHYS + 0x00017000)
#define TIA_BASE (IO_PHYS + 0x0001C000)
#define PMIF_SPI_BASE (IO_PHYS + 0x00024000)
#define PMICSPI_MST_BASE (IO_PHYS + 0x00025000)
#define PMIF_SPMI_BASE (IO_PHYS + 0x00027000)
#define SPMI_MST_BASE (IO_PHYS + 0x00029000)
#define DDRPHY_BASE (IO_PHYS + 0x00330000)
#define KPD_BASE (IO_PHYS + 0x00010000)
#define DEM_BASE (0x0D0A0000)
#define MCUSYS_CFGREG_BASE (0x0C530000)
//#define CA7MCUCFG_BASE (IO_PHYS + 0x00200100)
//#define CA15L_CONFIG_BASE (IO_PHYS + 0x00200200)
#define SRAMROM_BASE (IO_PHYS + 0x00214000)
#define GICD_BASE (0x0c000000)
#define GICR_BASE (0x0c040000)
#define AUXADC_BASE (IO_PHYS + 0X01002000)
#define DEVINFO_BASE (IO_PHYS + 0x01C10000)
#define UART0_BASE (IO_PHYS + 0x01001100)
#define UART1_BASE (IO_PHYS + 0x01001200)
#define UART2_BASE (IO_PHYS + 0x01001300)
#define UART3_BASE (IO_PHYS + 0x01001400)
#define SPI_BASE (IO_PHYS + 0x010F0000)
#define NFI_BASE (IO_PHYS + 0x0100D000) /* FIXME: not list in memory map */
#define NFIECC_BASE (IO_PHYS + 0x0100E000) /* FIXME: not list in memory map */
#define MSDC0_TOP_BASE (IO_PHYS + 0x01F50000)
#define MSDC1_TOP_BASE (IO_PHYS + 0x01E10000)
#define MSDC0_BASE (IO_PHYS + 0x01230000)
#define MSDC1_BASE (IO_PHYS + 0x01240000)
#define MSDC2_BASE (IO_PHYS + 0x01250000)
#define MSDC3_BASE (IO_PHYS + 0x01260000) /* Reserved in Sylvia */
#define U3D_BASE (IO_PHYS + 0x01200000) /* MAC: 0x1120_0000 */
#define USB_SIF_BASE (IO_PHYS + 0x01E40000) /* PHY: 0x11E4_0000 */
#define USB1P_SIF_BASE (IO_PHYS + 0x01C40000)
#define PCIE_BASE (IO_PHYS + 0x093F0000)
#define PCIE_PHY_BASE (IO_PHYS + 0x01E20000)
#define CPUXGPT_BASE (IO_PHYS + 0x00200000)
#define SUB_INFRACFG_AO_BASE (IO_PHYS + 0x0030E000)
/*=======================================================================*/
/* AP HW code offset */
/*=======================================================================*/
#define APHW_CODE (VER_BASE)
#define APHW_SUBCODE (VER_BASE + 0x04)
#define APHW_VER (VER_BASE + 0x08)
#define APSW_VER (VER_BASE + 0x0C)
// #define AMCONFG_BASE (0xFFFFFFFF)
/*=======================================================================*/
/* USB register offset */
/*=======================================================================*/
#define SSUSB_DEV_BASE (U3D_BASE + 0x1000) /* FIXME: not list in memory map */
#define SSUSB_EPCTL_CSR_BASE (U3D_BASE + 0x1800) /* FIXME: not list in memory map */
#define SSUSB_USB3_MAC_CSR_BASE (U3D_BASE + 0x2400) /* FIXME: not list in memory map */
#define SSUSB_USB3_SYS_CSR_BASE (U3D_BASE + 0x2400) /* FIXME: not list in memory map */
#define SSUSB_USB2_CSR_BASE (U3D_BASE + 0x3400) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_IPPC_BASE (U3D_BASE + 0x3E00) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_SPLLC_BASE (USB_SIF_BASE + 0x700) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_U2PHY_COM_BASE (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_U3PHYD_BASE (USB_SIF_BASE + 0x900) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */
#define SSUSB_USB30_PHYA_SIV_B2_BASE (USB_SIF_BASE + 0xA00) /* FIXME: not list in memory map */
#define SSUSB_USB30_PHYA_SIV_B_BASE (USB_SIF_BASE + 0xB00) /* FIXME: not list in memory map */
#define SSUSB_SIFSLV_U3PHYA_DA_BASE (USB_SIF_BASE + 0xC00) /* FIXME: not list in memory map */
/*=======================================================================*/
/* USB download control */
/*=======================================================================*/
#define SECURITY_AO (0x1001A000)
#define BOOT_MISC0 (SECURITY_AO + 0x0080)
#define MISC_LOCK_KEY (SECURITY_AO + 0x0100)
#define RST_CON (SECURITY_AO + 0x0108)
#define MISC_LOCK_KEY_MAGIC 0xAD98
#define USBDL_FLAG BOOT_MISC0
#define USBDL_BIT_EN (0x00000001) /* 1: download bit enabled */
#define USBDL_BROM (0x00000002) /* 0: usbdl by brom; 1: usbdl by bootloader */
#define USBDL_TIMEOUT_MASK (0x0000FFFC) /* 14-bit timeout: 0x0000~0x3FFE: second; 0x3FFFF: no timeout */
#define USBDL_TIMEOUT_MAX (USBDL_TIMEOUT_MASK >> 2) /* maximum timeout indicates no timeout */
#define USBDL_MAGIC (0x444C0000) /* Brom will check this magic number */
#define SRAMROM_USBDL_TO_DIS (SRAMROM_BASE + 0x0054)
#define USBDL_TO_DIS (0x00000001)
/*=======================================================================*/
/* NAND Control */
/*=======================================================================*/
#define NAND_PAGE_SIZE (2048) // (Bytes)
#define NAND_BLOCK_BLKS (64) // 64 nand pages = 128KB
#define NAND_PAGE_SHIFT (9)
#define NAND_LARGE_PAGE (11) // large page
#define NAND_SMALL_PAGE (9) // small page
#define NAND_BUS_WIDTH_8 (8)
#define NAND_BUS_WIDTH_16 (16)
#define NAND_FDM_SIZE (8)
#define NAND_ECC_SW (0)
#define NAND_ECC_HW (1)
#define NFI_MAX_FDM_SIZE (8)
#define NFI_MAX_FDM_SEC_NUM (8)
#define NFI_MAX_LOCK_CHANNEL (16)
#define ECC_MAX_CORRECTABLE_BITS (12)
#define ECC_MAX_PARITY_SIZE (20) /* in bytes */
#define ECC_ERR_LOCATION_MASK (0x1FFF)
#define ECC_ERR_LOCATION_SHIFT (16)
#define NAND_FFBUF_SIZE (2048 + 64)
/*=======================================================================*/
/* SW Reset Vector */
/*=======================================================================*/
/* setup the reset vector base address after warm reset to Aarch64 */
#define RVBADDRESS_CPU0 (MCUSYS_CFGREG_BASE + 0xC900)
/* IRQ */
#define SYS_TIMER_IRQ (233 + 32)
#define GZ_SW_IRQ (513 + 32)
#endif

472
src/vendorcode/mediatek/mt8195/include/pll.h Normal file
View File

@@ -0,0 +1,472 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to MediaTek Inc. and/or its licensors. Without
* the prior written permission of MediaTek inc. and/or its licensors, any
* reproduction, modification, use or disclosure of MediaTek Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
* SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
* RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
* MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek
* Software") have been modified by MediaTek Inc. All revisions are subject to
* any receiver's applicable license agreements with MediaTek Inc.
*/
#ifndef PLL_H
#define PLL_H
#include "mt8195.h"
/* for MTCMOS bus protection */
//TODO
#define INFRA_TOPAXI_PROTECTEN (INFRACFG_AO_BASE + 0x0220)
#define INFRA_TOPAXI_PROTECTEN_SET (INFRACFG_AO_BASE + 0x02A0)
#define INFRA_TOPAXI_PROTECTEN_CLR (INFRACFG_AO_BASE + 0x02A4)
#define INFRA_TOPAXI_PROTECTEN_STA0 (INFRACFG_AO_BASE + 0x0224)
#define INFRA_TOPAXI_PROTECTEN_STA1 (INFRACFG_AO_BASE + 0x0228)
#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x0250)
#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x02A8)
#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x02AC)
#define INFRA_TOPAXI_PROTECTEN_STA0_1 (INFRACFG_AO_BASE + 0x0254)
#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x0258)
#define INFRA_TOPAXI_PROTECTEN_MCU (INFRACFG_AO_BASE + 0x02C0)
#define INFRA_TOPAXI_PROTECTEN_MCU_STA0 (INFRACFG_AO_BASE + 0x02E0)
#define INFRA_TOPAXI_PROTECTEN_MCU_STA1 (INFRACFG_AO_BASE + 0x02E4)
#define INFRA_TOPAXI_PROTECTEN_MCU_SET (INFRACFG_AO_BASE + 0x02C4)
#define INFRA_TOPAXI_PROTECTEN_MCU_CLR (INFRACFG_AO_BASE + 0x02C8)
#define INFRA_TOPAXI_PROTECTEN_MM (INFRACFG_AO_BASE + 0x02D0)
#define INFRA_TOPAXI_PROTECTEN_MM_SET (INFRACFG_AO_BASE + 0x02D4)
#define INFRA_TOPAXI_PROTECTEN_MM_CLR (INFRACFG_AO_BASE + 0x02D8)
#define INFRA_TOPAXI_PROTECTEN_MM_STA0 (INFRACFG_AO_BASE + 0x02E8)
#define INFRA_TOPAXI_PROTECTEN_MM_STA1 (INFRACFG_AO_BASE + 0x02EC)
#define INFRA_TOPAXI_PROTECTEN_2 (INFRACFG_AO_BASE + 0x0710)
#define INFRA_TOPAXI_PROTECTEN_2_SET (INFRACFG_AO_BASE + 0x0714)
#define INFRA_TOPAXI_PROTECTEN_2_CLR (INFRACFG_AO_BASE + 0x0718)
#define INFRA_TOPAXI_PROTECTEN_STA0_2 (INFRACFG_AO_BASE + 0x0720)
#define INFRA_TOPAXI_PROTECTEN_STA1_2 (INFRACFG_AO_BASE + 0x0724)
#define INFRA_TOPAXI_PROTECTEN_MM_2 (INFRACFG_AO_BASE + 0x0DC8)
#define INFRA_TOPAXI_PROTECTEN_MM_2_SET (INFRACFG_AO_BASE + 0x0DCC)
#define INFRA_TOPAXI_PROTECTEN_MM_2_CLR (INFRACFG_AO_BASE + 0x0DD0)
#define INFRA_TOPAXI_PROTECTEN_MM_2_STA0 (INFRACFG_AO_BASE + 0x0DD4)
#define INFRA_TOPAXI_PROTECTEN_MM_2_STA1 (INFRACFG_AO_BASE + 0x0DD8)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR (INFRACFG_AO_BASE + 0x0B80)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET (INFRACFG_AO_BASE + 0x0B84)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR (INFRACFG_AO_BASE + 0x0B88)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0 (INFRACFG_AO_BASE + 0x0B8c)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1 (INFRACFG_AO_BASE + 0x0B90)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1 (INFRACFG_AO_BASE + 0x0BA0)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_SET (INFRACFG_AO_BASE + 0x0BA4)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_CLR (INFRACFG_AO_BASE + 0x0BA8)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0 (INFRACFG_AO_BASE + 0x0BAc)
#define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1 (INFRACFG_AO_BASE + 0x0BB0)
#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR (INFRACFG_AO_BASE + 0x0BB4)
#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_SET (INFRACFG_AO_BASE + 0x0BB8)
#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_CLR (INFRACFG_AO_BASE + 0x0BBC)
#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0 (INFRACFG_AO_BASE + 0x0BC0)
#define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1 (INFRACFG_AO_BASE + 0x0BC4)
/* MCUCFG Register */
#define CPU_PLLDIV_CFG0 (MCUCFG_BASE + 0xA2A0)
#define CPU_PLLDIV_CFG1 (MCUCFG_BASE + 0xA2A4)
#define BUS_PLLDIV_CFG (MCUCFG_BASE + 0xA2E0)
/* APMIXEDSYS Register */
#define AP_PLL_CON0 (APMIXED_BASE + 0x0000)
#define PLLON_CON0 (APMIXED_BASE + 0x0050)
#define PLLON_CON1 (APMIXED_BASE + 0x0054)
#define PLLON_CON2 (APMIXED_BASE + 0x0058)
#define PLLON_CON3 (APMIXED_BASE + 0x005C)
#define ARMPLL_LL_CON0 (APMIXED_BASE + 0x0020)
#define ARMPLL_LL_CON1 (APMIXED_BASE + 0x0024)
#define ARMPLL_LL_CON2 (APMIXED_BASE + 0x0028)
#define ARMPLL_LL_CON3 (APMIXED_BASE + 0x002C)
#define ARMPLL_LL_CON4 (APMIXED_BASE + 0X0600)
#define ARMPLL_BL_CON0 (APMIXED_BASE + 0X0070)
#define ARMPLL_BL_CON1 (APMIXED_BASE + 0X0074)
#define ARMPLL_BL_CON2 (APMIXED_BASE + 0X0078)
#define ARMPLL_BL_CON3 (APMIXED_BASE + 0X007C)
#define ARMPLL_BL_CON4 (APMIXED_BASE + 0X0080)
#define CCIPLL_CON0 (APMIXED_BASE + 0X0030)
#define CCIPLL_CON1 (APMIXED_BASE + 0X0634)
#define CCIPLL_CON2 (APMIXED_BASE + 0X0638)
#define CCIPLL_CON3 (APMIXED_BASE + 0X063C)
#define CCIPLL_CON4 (APMIXED_BASE + 0X0640)
#define NNAPLL_CON0 (APMIXED_BASE + 0X0390)
#define NNAPLL_CON1 (APMIXED_BASE + 0X0394)
#define NNAPLL_CON2 (APMIXED_BASE + 0X0398)
#define NNAPLL_CON3 (APMIXED_BASE + 0X039C)
#define NNAPLL_CON4 (APMIXED_BASE + 0X03A0)
#define RESPLL_CON0 (APMIXED_BASE + 0X0190)
#define RESPLL_CON1 (APMIXED_BASE + 0X0194)
#define RESPLL_CON2 (APMIXED_BASE + 0X0198)
#define RESPLL_CON3 (APMIXED_BASE + 0X019C)
#define RESPLL_CON4 (APMIXED_BASE + 0X0320)
#define ETHPLL_CON0 (APMIXED_BASE + 0X0360)
#define ETHPLL_CON1 (APMIXED_BASE + 0X0364)
#define ETHPLL_CON2 (APMIXED_BASE + 0X0368)
#define ETHPLL_CON3 (APMIXED_BASE + 0X036C)
#define ETHPLL_CON4 (APMIXED_BASE + 0X0370)
#define MSDCPLL_CON0 (APMIXED_BASE + 0X0710)
#define MSDCPLL_CON1 (APMIXED_BASE + 0X0714)
#define MSDCPLL_CON2 (APMIXED_BASE + 0X0718)
#define MSDCPLL_CON3 (APMIXED_BASE + 0X071C)
#define MSDCPLL_CON4 (APMIXED_BASE + 0X0720)
#define TVDPLL1_CON0 (APMIXED_BASE + 0X00A0)
#define TVDPLL1_CON1 (APMIXED_BASE + 0X00A4)
#define TVDPLL1_CON2 (APMIXED_BASE + 0X00A8)
#define TVDPLL1_CON3 (APMIXED_BASE + 0X00AC)
#define TVDPLL1_CON4 (APMIXED_BASE + 0X00B0)
#define TVDPLL2_CON0 (APMIXED_BASE + 0X00C0)
#define TVDPLL2_CON1 (APMIXED_BASE + 0X00C4)
#define TVDPLL2_CON2 (APMIXED_BASE + 0X00C8)
#define TVDPLL2_CON3 (APMIXED_BASE + 0X00CC)
#define TVDPLL2_CON4 (APMIXED_BASE + 0X00D0)
#define MPLL_CON0 (APMIXED_BASE + 0X0800)
#define MPLL_CON1 (APMIXED_BASE + 0X0804)
#define MPLL_CON2 (APMIXED_BASE + 0X0808)
#define MPLL_CON3 (APMIXED_BASE + 0X080C)
#define MPLL_CON4 (APMIXED_BASE + 0X0810)
#define MMPLL_CON0 (APMIXED_BASE + 0X00E0)
#define MMPLL_CON1 (APMIXED_BASE + 0X00E4)
#define MMPLL_CON2 (APMIXED_BASE + 0X00E8)
#define MMPLL_CON3 (APMIXED_BASE + 0X00EC)
#define MMPLL_CON4 (APMIXED_BASE + 0X00F0)
#define MAINPLL_CON0 (APMIXED_BASE + 0X01D0)
#define MAINPLL_CON1 (APMIXED_BASE + 0X01D4)
#define MAINPLL_CON2 (APMIXED_BASE + 0X01D8)
#define MAINPLL_CON3 (APMIXED_BASE + 0X01DC)
#define MAINPLL_CON4 (APMIXED_BASE + 0X01E0)
#define VDECPLL_CON0 (APMIXED_BASE + 0X0890)
#define VDECPLL_CON1 (APMIXED_BASE + 0X0894)
#define VDECPLL_CON2 (APMIXED_BASE + 0X0898)
#define VDECPLL_CON3 (APMIXED_BASE + 0X089C)
#define VDECPLL_CON4 (APMIXED_BASE + 0X08A0)
#define IMGPLL_CON0 (APMIXED_BASE + 0X0100)
#define IMGPLL_CON1 (APMIXED_BASE + 0X0104)
#define IMGPLL_CON2 (APMIXED_BASE + 0X0108)
#define IMGPLL_CON3 (APMIXED_BASE + 0X010C)
#define IMGPLL_CON4 (APMIXED_BASE + 0X0110)
#define UNIVPLL_CON0 (APMIXED_BASE + 0X01F0)
#define UNIVPLL_CON1 (APMIXED_BASE + 0X01F4)
#define UNIVPLL_CON2 (APMIXED_BASE + 0X01F8)
#define UNIVPLL_CON3 (APMIXED_BASE + 0X01FC)
#define UNIVPLL_CON4 (APMIXED_BASE + 0X0700)
#define HDMIPLL1_CON0 (APMIXED_BASE + 0X08C0)
#define HDMIPLL1_CON1 (APMIXED_BASE + 0X08C4)
#define HDMIPLL1_CON2 (APMIXED_BASE + 0X08C8)
#define HDMIPLL1_CON3 (APMIXED_BASE + 0X08CC)
#define HDMIPLL1_CON4 (APMIXED_BASE + 0X08D0)
#define HDMIPLL2_CON0 (APMIXED_BASE + 0X0870)
#define HDMIPLL2_CON1 (APMIXED_BASE + 0X0874)
#define HDMIPLL2_CON2 (APMIXED_BASE + 0X0878)
#define HDMIPLL2_CON3 (APMIXED_BASE + 0X087C)
#define HDMIPLL2_CON4 (APMIXED_BASE + 0X0880)
#define HDMIRX_APLL_CON0 (APMIXED_BASE + 0X08E0)
#define HDMIRX_APLL_CON1 (APMIXED_BASE + 0X08E4)
#define HDMIRX_APLL_CON2 (APMIXED_BASE + 0X08E8)
#define HDMIRX_APLL_CON3 (APMIXED_BASE + 0X08EC)
#define HDMIRX_APLL_CON4 (APMIXED_BASE + 0X08F0)
#define HDMIRX_APLL_CON5 (APMIXED_BASE + 0X0DD4)
#define USB1PLL_CON0 (APMIXED_BASE + 0X01A0)
#define USB1PLL_CON1 (APMIXED_BASE + 0X01A4)
#define USB1PLL_CON2 (APMIXED_BASE + 0X01A8)
#define USB1PLL_CON3 (APMIXED_BASE + 0X01AC)
#define USB1PLL_CON4 (APMIXED_BASE + 0X01B0)
#define ADSPPLL_CON0 (APMIXED_BASE + 0X07E0)
#define ADSPPLL_CON1 (APMIXED_BASE + 0X07E4)
#define ADSPPLL_CON2 (APMIXED_BASE + 0X07E8)
#define ADSPPLL_CON3 (APMIXED_BASE + 0X07EC)
#define ADSPPLL_CON4 (APMIXED_BASE + 0X07F0)
#define APLL1_CON0 (APMIXED_BASE + 0X07C0)
#define APLL1_CON1 (APMIXED_BASE + 0X07C4)
#define APLL1_CON2 (APMIXED_BASE + 0X07C8)
#define APLL1_CON3 (APMIXED_BASE + 0X07CC)
#define APLL1_CON4 (APMIXED_BASE + 0X07D0)
#define APLL1_CON5 (APMIXED_BASE + 0X0DC0)
#define APLL2_CON0 (APMIXED_BASE + 0X0780)
#define APLL2_CON1 (APMIXED_BASE + 0X0784)
#define APLL2_CON2 (APMIXED_BASE + 0X0788)
#define APLL2_CON3 (APMIXED_BASE + 0X078C)
#define APLL2_CON4 (APMIXED_BASE + 0X0790)
#define APLL2_CON5 (APMIXED_BASE + 0X0DC4)
#define APLL3_CON0 (APMIXED_BASE + 0X0760)
#define APLL3_CON1 (APMIXED_BASE + 0X0764)
#define APLL3_CON2 (APMIXED_BASE + 0X0768)
#define APLL3_CON3 (APMIXED_BASE + 0X076C)
#define APLL3_CON4 (APMIXED_BASE + 0X0770)
#define APLL3_CON5 (APMIXED_BASE + 0X0DC8)
#define APLL4_CON0 (APMIXED_BASE + 0X0740)
#define APLL4_CON1 (APMIXED_BASE + 0X0744)
#define APLL4_CON2 (APMIXED_BASE + 0X0748)
#define APLL4_CON3 (APMIXED_BASE + 0X074C)
#define APLL4_CON4 (APMIXED_BASE + 0X0750)
#define APLL4_CON5 (APMIXED_BASE + 0X0DCC)
#define APLL5_CON0 (APMIXED_BASE + 0X07A0)
#define APLL5_CON1 (APMIXED_BASE + 0X07A4)
#define APLL5_CON2 (APMIXED_BASE + 0X07A8)
#define APLL5_CON3 (APMIXED_BASE + 0X07AC)
#define APLL5_CON4 (APMIXED_BASE + 0X07B0)
#define APLL5_CON5 (APMIXED_BASE + 0X0DD0)
#define MFGPLL_CON0 (APMIXED_BASE + 0X0340)
#define MFGPLL_CON1 (APMIXED_BASE + 0X0344)
#define MFGPLL_CON2 (APMIXED_BASE + 0X0348)
#define MFGPLL_CON3 (APMIXED_BASE + 0X034C)
#define MFGPLL_CON4 (APMIXED_BASE + 0X0350)
#define DGIPLL_CON0 (APMIXED_BASE + 0X0150)
#define DGIPLL_CON1 (APMIXED_BASE + 0X0154)
#define DGIPLL_CON2 (APMIXED_BASE + 0X0158)
#define DGIPLL_CON3 (APMIXED_BASE + 0X015C)
#define DGIPLL_CON4 (APMIXED_BASE + 0X0160)
#define APLL1_TUNER_CON0 (APMIXED_BASE + 0x0470)
#define APLL2_TUNER_CON0 (APMIXED_BASE + 0x0474)
#define APLL3_TUNER_CON0 (APMIXED_BASE + 0x0478)
#define APLL4_TUNER_CON0 (APMIXED_BASE + 0x047C)
#define APLL5_TUNER_CON0 (APMIXED_BASE + 0x0480)
/* TOPCKGEN Register */
#define CLK_CFG_UPDATE (TOPCKGEN_BASE + 0x004)
#define CLK_CFG_UPDATE1 (TOPCKGEN_BASE + 0x008)
#define CLK_CFG_UPDATE2 (TOPCKGEN_BASE + 0x00C)
#define CLK_CFG_UPDATE3 (TOPCKGEN_BASE + 0x010)
#define CLK_CFG_UPDATE4 (TOPCKGEN_BASE + 0x014)
#define CLK_CFG_0_SET (TOPCKGEN_BASE + 0x024)
#define CLK_CFG_0_CLR (TOPCKGEN_BASE + 0x028)
#define CLK_CFG_1_SET (TOPCKGEN_BASE + 0x030)
#define CLK_CFG_1_CLR (TOPCKGEN_BASE + 0x034)
#define CLK_CFG_2_SET (TOPCKGEN_BASE + 0x03C)
#define CLK_CFG_2_CLR (TOPCKGEN_BASE + 0x040)
#define CLK_CFG_3_SET (TOPCKGEN_BASE + 0x048)
#define CLK_CFG_3_CLR (TOPCKGEN_BASE + 0x04C)
#define CLK_CFG_4_SET (TOPCKGEN_BASE + 0x054)
#define CLK_CFG_4_CLR (TOPCKGEN_BASE + 0x058)
#define CLK_CFG_5_SET (TOPCKGEN_BASE + 0x060)
#define CLK_CFG_5_CLR (TOPCKGEN_BASE + 0x064)
#define CLK_CFG_6_SET (TOPCKGEN_BASE + 0x06C)
#define CLK_CFG_6_CLR (TOPCKGEN_BASE + 0x070)
#define CLK_CFG_7_SET (TOPCKGEN_BASE + 0x078)
#define CLK_CFG_7_CLR (TOPCKGEN_BASE + 0x07C)
#define CLK_CFG_8_SET (TOPCKGEN_BASE + 0x084)
#define CLK_CFG_8_CLR (TOPCKGEN_BASE + 0x088)
#define CLK_CFG_9_SET (TOPCKGEN_BASE + 0x090)
#define CLK_CFG_9_CLR (TOPCKGEN_BASE + 0x094)
#define CLK_CFG_10_SET (TOPCKGEN_BASE + 0x09C)
#define CLK_CFG_10_CLR (TOPCKGEN_BASE + 0x0A0)
#define CLK_CFG_11_SET (TOPCKGEN_BASE + 0x0A8)
#define CLK_CFG_11_CLR (TOPCKGEN_BASE + 0x0AC)
#define CLK_CFG_12_SET (TOPCKGEN_BASE + 0x0B4)
#define CLK_CFG_12_CLR (TOPCKGEN_BASE + 0x0B8)
#define CLK_CFG_13_SET (TOPCKGEN_BASE + 0x0C0)
#define CLK_CFG_13_CLR (TOPCKGEN_BASE + 0x0C4)
#define CLK_CFG_14_SET (TOPCKGEN_BASE + 0x0CC)
#define CLK_CFG_14_CLR (TOPCKGEN_BASE + 0x0D0)
#define CLK_CFG_15_SET (TOPCKGEN_BASE + 0x0D8)
#define CLK_CFG_15_CLR (TOPCKGEN_BASE + 0x0DC)
#define CLK_CFG_16_SET (TOPCKGEN_BASE + 0x0E4)
#define CLK_CFG_16_CLR (TOPCKGEN_BASE + 0x0E8)
#define CLK_CFG_17_SET (TOPCKGEN_BASE + 0x0F0)
#define CLK_CFG_17_CLR (TOPCKGEN_BASE + 0x0F4)
#define CLK_CFG_18_SET (TOPCKGEN_BASE + 0x0FC)
#define CLK_CFG_18_CLR (TOPCKGEN_BASE + 0x0100)
#define CLK_CFG_19_SET (TOPCKGEN_BASE + 0x0108)
#define CLK_CFG_19_CLR (TOPCKGEN_BASE + 0x010C)
#define CLK_CFG_20_SET (TOPCKGEN_BASE + 0x0114)
#define CLK_CFG_20_CLR (TOPCKGEN_BASE + 0x0118)
#define CLK_CFG_21_SET (TOPCKGEN_BASE + 0x0120)
#define CLK_CFG_21_CLR (TOPCKGEN_BASE + 0x0124)
#define CLK_CFG_22_SET (TOPCKGEN_BASE + 0x012C)
#define CLK_CFG_22_CLR (TOPCKGEN_BASE + 0x0130)
#define CLK_CFG_23_SET (TOPCKGEN_BASE + 0x0138)
#define CLK_CFG_23_CLR (TOPCKGEN_BASE + 0x013C)
#define CLK_CFG_24_SET (TOPCKGEN_BASE + 0x0144)
#define CLK_CFG_24_CLR (TOPCKGEN_BASE + 0x0148)
#define CLK_CFG_25_SET (TOPCKGEN_BASE + 0x0150)
#define CLK_CFG_25_CLR (TOPCKGEN_BASE + 0x0154)
#define CLK_CFG_26_SET (TOPCKGEN_BASE + 0x015C)
#define CLK_CFG_26_CLR (TOPCKGEN_BASE + 0x0160)
#define CLK_CFG_27_SET (TOPCKGEN_BASE + 0x0168)
#define CLK_CFG_27_CLR (TOPCKGEN_BASE + 0x016C)
#define CLK_CFG_28_SET (TOPCKGEN_BASE + 0x0174)
#define CLK_CFG_28_CLR (TOPCKGEN_BASE + 0x0178)
#define CLK_CFG_29_SET (TOPCKGEN_BASE + 0x0180)
#define CLK_CFG_29_CLR (TOPCKGEN_BASE + 0x0184)
#define CLK_CFG_30_SET (TOPCKGEN_BASE + 0x018C)
#define CLK_CFG_30_CLR (TOPCKGEN_BASE + 0x0190)
#define CLK_CFG_31_SET (TOPCKGEN_BASE + 0x0198)
#define CLK_CFG_31_CLR (TOPCKGEN_BASE + 0x019C)
#define CLK_CFG_32_SET (TOPCKGEN_BASE + 0x01A4)
#define CLK_CFG_32_CLR (TOPCKGEN_BASE + 0x01A8)
#define CLK_CFG_33_SET (TOPCKGEN_BASE + 0x01B0)
#define CLK_CFG_33_CLR (TOPCKGEN_BASE + 0x01B4)
#define CLK_CFG_34_SET (TOPCKGEN_BASE + 0x01BC)
#define CLK_CFG_34_CLR (TOPCKGEN_BASE + 0x01C0)
#define CLK_CFG_35_SET (TOPCKGEN_BASE + 0x01C8)
#define CLK_CFG_35_CLR (TOPCKGEN_BASE + 0x01CC)
#define CLK_CFG_36_SET (TOPCKGEN_BASE + 0x01D4)
#define CLK_CFG_36_CLR (TOPCKGEN_BASE + 0x01D8)
#define CLK_CFG_37_SET (TOPCKGEN_BASE + 0x01E0)
#define CLK_CFG_37_CLR (TOPCKGEN_BASE + 0x01E4)
#define CLK_MISC_CFG_3 (TOPCKGEN_BASE + 0x0250)
#define CLK_DBG_CFG (TOPCKGEN_BASE + 0x020C)
#define CLK26CALI_0 (TOPCKGEN_BASE + 0x0218)
#define CLK26CALI_1 (TOPCKGEN_BASE + 0x021C)
#define CLK_MISC_CFG_0 (TOPCKGEN_BASE + 0x022C)
#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x0264)
#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70)
#define VDNR_DCM_TOP_INFRA_CTRL0 (INFRA_AO_BCRM_BASE + 0x034)
#define TOPCKGEN_CLK_MISC_CFG_1 (TOPCKGEN_BASE + 0x238)
#define TOPCKGEN_CLK_MISC_CFG_3 (TOPCKGEN_BASE + 0x250)
#define INFRACFG_AO_MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE + 0x84)
#define INFRACFG_AO_MODULE_SW_CG_1_CLR (INFRACFG_AO_BASE + 0x8c)
#define INFRACFG_AO_MODULE_SW_CG_2_CLR (INFRACFG_AO_BASE + 0xa8)
#define INFRACFG_AO_MODULE_SW_CG_3_CLR (INFRACFG_AO_BASE + 0xc4)
#define INFRACFG_AO_MODULE_SW_CG_4_CLR (INFRACFG_AO_BASE + 0xe4)
#define APMIXEDSYS_AP_PLL_CON2 (APMIXED_BASE + 0x8)
#define IPNNA_F26M_CK_CG (IPNNA_BASE + 0x104)
#define IPNNA_AXI_CK_CG (IPNNA_BASE + 0x110)
#define IPNNA_NNA0_CG_EN (IPNNA_BASE + 0x90)
#define IPNNA_NNA1_CG_EN (IPNNA_BASE + 0x94)
#define IPNNA_NNA0_EMI_CG_EN (IPNNA_BASE + 0x98)
#define IPNNA_NNA1_EMI_CG_EN (IPNNA_BASE + 0x9c)
#define IPNNA_NNA0_AXI_CG_EN (IPNNA_BASE + 0xa0)
#define IPNNA_NNA1_AXI_CG_EN (IPNNA_BASE + 0xa4)
#define SCP_PAR_TOP_AUDIODSP_CK_CG (SCP_PAR_TOP_BASE + 0x180)
#define AUDIO_AUDIO_TOP_0 (AUDIO_BASE + 0x0)
#define AUDIO_AUDIO_TOP_4 (AUDIO_BASE + 0x10)
#define AUDIO_AUDIO_TOP_5 (AUDIO_BASE + 0x14)
#define AUDIO_AUDIO_TOP_6 (AUDIO_BASE + 0x18)
#define AUDIO_AUDIO_TOP_1 (AUDIO_BASE + 0x4)
#define AUDIO_AUDIO_TOP_3 (AUDIO_BASE + 0xc)
#define AUDIO_SRC_MEM_ASRC_TOP_1 (AUDIO_SRC_BASE + 0x1004)
#define PERICFG_AO_PERI_MODULE_SW_CG_0_SET (PERICFG_AO_BASE + 0x10)
#define PERICFG_AO_PERI_MODULE_SW_CG_0_CLR (PERICFG_AO_BASE + 0x14)
#define MFGCFG_MFG_CG_CLR (MFGCFG_BASE + 0x8)
#define VPP0_REG_VPPSYS0_CG0_CLR (VPP0_REG_BASE + 0x28)
#define VPP0_REG_VPPSYS0_CG1_CLR (VPP0_REG_BASE + 0x34)
#define VPP0_REG_VPPSYS0_CG2_CLR (VPP0_REG_BASE + 0x40)
#define WPESYS_TOP_REG_WPESYS_RG_000 (WPESYS_TOP_REG_BASE + 0x0)
#define WPE_VPP0_CTL_WPE_DCM_DIS (WPE_VPP0_BASE + 0x58)
#define WPE_VPP0_CTL_DMA_DCM_DIS (WPE_VPP0_BASE + 0x5c)
#define WPE_VPP1_CTL_WPE_DCM_DIS (WPE_VPP1_BASE + 0x58)
#define WPE_VPP1_CTL_DMA_DCM_DIS (WPE_VPP1_BASE + 0x5c)
#define VPPSYS1_CONFIG_VPPSYS1_CG_0_CLR (VPPSYS1_CONFIG_BASE + 0x108)
#define VPPSYS1_CONFIG_VPPSYS1_CG_1_CLR (VPPSYS1_CONFIG_BASE + 0x118)
#define IMGSYS_MAIN_IMG_MAIN_CG_CLR (IMGSYS_MAIN_BASE + 0x8)
#define IMGSYS1_DIP_TOP_MACRO_CG_CLR (IMGSYS1_DIP_TOP_BASE + 0x8)
#define IMGSYS1_DIP_NR_MACRO_CG_CLR (IMGSYS1_DIP_NR_BASE + 0x8)
#define IMGSYS1_WPE_MACRO_CG_CLR (IMGSYS1_WPE_BASE + 0x8)
#define IPESYS_MACRO_CG (IPESYS_BASE + 0x0)
#define CAMSYS_MAIN_CAMSYS_CG_CLR (CAMSYS_MAIN_BASE + 0x8)
#define CAMSYS_RAWA_CAMSYS_CG_CLR (CAMSYS_RAWA_BASE + 0x8)
#define CAMSYS_YUVA_CAMSYS_CG_CLR (CAMSYS_YUVA_BASE + 0x8)
#define CAMSYS_RAWB_CAMSYS_CG_CLR (CAMSYS_RAWB_BASE + 0x8)
#define CAMSYS_YUVB_CAMSYS_CG_CLR (CAMSYS_YUVB_BASE + 0x8)
#define CAMSYS_MRAW_CAMSYS_CG_CLR (CAMSYS_MRAW_BASE + 0x8)
#define CCU_MAIN_CCUSYS_CG_CLR (CCU_MAIN_BASE + 0x8)
#define VDEC_SOC_GCON_VDEC_CKEN (VDEC_SOC_GCON_BASE + 0x0)
#define VDEC_SOC_GCON_LAT_CKEN (VDEC_SOC_GCON_BASE + 0x200)
#define VDEC_SOC_GCON_LARB_CKEN_CON (VDEC_SOC_GCON_BASE + 0x8)
#define VDEC_GCON_VDEC_CKEN (VDEC_GCON_BASE + 0x0)
#define VDEC_GCON_LAT_CKEN (VDEC_GCON_BASE + 0x200)
#define VDEC_GCON_LARB_CKEN_CON (VDEC_GCON_BASE + 0x8)
#define VDEC_CORE1_GCON_VDEC_CKEN (VDEC_CORE1_GCON_BASE + 0x0)
#define VDEC_CORE1_GCON_LAT_CKEN (VDEC_CORE1_GCON_BASE + 0x200)
#define VDEC_CORE1_GCON_LARB_CKEN_CON (VDEC_CORE1_GCON_BASE + 0x8)
#define VENC_GCON_VENCSYS_CG_SET (VENC_GCON_BASE + 0x4)
#define VENC_CORE1_GCON_VENCSYS_CG_SET (VENC_CORE1_GCON_BASE + 0x4)
#define VDOSYS0_CONFIG_GLOBAL0_CG_0_CLR (VDOSYS0_CONFIG_BASE + 0x108)
#define VDOSYS0_CONFIG_GLOBAL0_CG_1_CLR (VDOSYS0_CONFIG_BASE + 0x118)
#define VDOSYS0_CONFIG_GLOBAL0_CG_2_CLR (VDOSYS0_CONFIG_BASE + 0x128)
#define VDOSYS0_CONFIG_GLOBAL1_CG_0_CLR (VDOSYS0_CONFIG_BASE + 0x308)
#define VDOSYS0_CONFIG_GLOBAL1_CG_1_CLR (VDOSYS0_CONFIG_BASE + 0x318)
#define VDOSYS0_CONFIG_GLOBAL1_CG_2_CLR (VDOSYS0_CONFIG_BASE + 0x328)
#define VDOSYS1_CONFIG_VDOSYS1_CG_0_CLR (VDOSYS1_CONFIG_BASE + 0x108)
#define VDOSYS1_CONFIG_VDOSYS1_CG_1_CLR (VDOSYS1_CONFIG_BASE + 0x128)
#define VDOSYS1_CONFIG_VDOSYS1_CG_2_CLR (VDOSYS1_CONFIG_BASE + 0x138)
#define VDOSYS1_CONFIG_VDOSYS1_CG_3_CLR (VDOSYS1_CONFIG_BASE + 0x148)
#define AP_MDSRC_REQ (SPM_BASE + 0x43C)
/* CPU Freq Boost*/
enum cpu_opp {
CPU_OPP0 = 0,
CPU_OPP1,
CPU_OPP2,
CPU_OPP3,
CPU_OPP4,
CPU_OPP5,
CPU_OPP_NUM,
};
/*
* EXTERN FUNCTIONS
*/
extern unsigned int mt_get_abist_freq(unsigned int ID);
extern unsigned int mt_get_cpu_freq(void);
extern void set_armpll_ll_rate(enum cpu_opp opp);
extern void mt_set_topck_default(void);
#endif

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src/vendorcode/mediatek/mt8195/include/print.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef PRINT_H
#define PRINT_H
#include <console/console.h>
//int print(const char *fmt, ...);
#define print(_x_...) printk(BIOS_INFO, _x_)
#define printf print
#endif

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src/vendorcode/mediatek/mt8195/include/reg.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef REG_H
#define REG_H
#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
#define read32(addr) (*REG32(addr))
#define write32(addr, val) (*REG32(addr) = (val))
#endif

315
src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h Normal file
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#ifndef __SV_C_DATA_TRAFFIC_H
#define __SV_C_DATA_TRAFFIC_H
#if FOR_DV_SIMULATION_USED
#ifndef STRINGIFY(x)
#define STRINGIFY(x) #x
#endif
#endif
#define TOSTRING(x) STRINGIFY(x)
#define print_svarg(arg) \
({ \
mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \
})
/*
* channel type from sv's view
*/
enum {
SV_CHN_A = 0,
SV_CHN_B
};
/*
* dram type from sv's view
*/
enum {
SV_LPDDR = 0,
SV_LPDDR2,
SV_PCDDR3,
SV_LPDDR3,
SV_LPDDR4,
SV_LPDDR5
};
/*
* data rate from sv's view
*/
enum {
SV_DDR4266 = 0,
SV_DDR3200,
SV_DDR1600,
SV_DDR3733,
SV_DDR2400,
SV_DDR1866,
SV_DDR1200,
SV_DDR1333,
SV_DDR800,
SV_DDR1066,
SV_DDR2667,
SV_DDR4800,
SV_DDR5500,
SV_DDR6000,
SV_DDR6400,
SV_DDR2750,
SV_DDR2133
};
/*
* cal_sv_rand_args is data traffic from sv to c.
* sv randomizes these arguments for c to control
* calibration.
*/
typedef struct cal_sv_rand_args {
/* >>>>>>>>>> common part begin>>>>>>>>>> */
/*
* 0x4C503435
* "LP45"
*/
int magic;
/*
* 0: channel-a
* 1: channel-b
*/
int calibration_channel;
/*
* 0: rank0
* 1: rank1
*/
int calibration_rank;
/*
* 0: LPDDR
* 1: LPDDR2
* 2: PCDDR3
* 3: LPDDR3
* 4: LPDDR4
* 5: LPDDR5
*/
int dram_type;
/*
* 0: DDR4266
* 1: DDR3200
* 2: DDR1600
* 3: DDR3733
* 4: DDR2400
* 5: DDR1866
* 6: DDR1200
* 7: DDR1333
* 8: DDR800
* 9: DDR1066
* 10: DDR2667
* 11: DDR4800
* 12: DDR5500
* 13: DDR6000
* 14: DDR6400
* 15: DDR2750
* 16: DDR2133
*/
int datarate;
/*
* Data Mask Disable
* 0: enable
* 1: disable
*/
int dmd;
int mr2_value; /* for lp4-wirteleveling*/
int mr3_value;
int mr13_value;
int mr12_value;
int mr16_value;
int mr18_value; /* lp5 writeleveling */
int mr20_value; /* lp5 rddqc */
/* ============================= */
/* >>>>>>>>>> cbt part begin>>>>>>>>>> */
/*
* 0: doesn't run cbt calibration
* 1: run cbt calibration
*/
int cbt;
/*
* 0: rising phase
* 1: falling phase
*/
int cbt_phase;
/*
* 0: training mode1
* 1: training mode2
*/
int cbt_training_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk0_cbt_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk1_cbt_mode;
/*
* 0: cbt does NOT use autok
* 1: cbt use autok
*/
int cbt_autok;
/*
* autok respi
* 0/1/2/3
*/
int cbt_atk_respi;
/*
* 0: cbt does NOT use new cbt mode
* 1: cbt use new cbt mode
*/
int new_cbt_mode;
/*
* cbt pat0~7v
*/
int pat_v[8];
/*
* cbt pat0~7a
*/
int pat_a[8];
/*
* cbt pat_dmv
*/
int pat_dmv;
/*
* cbt pat_dma
*/
int pat_dma;
/*
* cbt pat_cs
*/
int pat_cs;
/*
* new cbt cagolden sel
*/
int cagolden_sel;
/*
* new cbt invert num
*/
int invert_num;
/* ============================= */
/* >>>>>>>>>> wl part begin>>>>>>>>>> */
/*
* 0: doesn't run wl calibration
* 1: run wl calibration
*/
int wl;
/*
* 0: wl does NOT use autok
* 1: wl use autok
*/
int wl_autok;
/*
* autok respi
* 0/1/2/3
*/
int wl_atk_respi;
/* ============================= */
/* >>>>>>>>>> Gating part begin >>>>>> */
/*
* 0: does not run gating calibration
* 1: run gating calibration
*/
int gating;
/*
* 0: SW mode calibration
* 1: HW AUTO calibration
*/
int gating_autok;
int dqsien_autok_pi_offset;
int dqsien_autok_early_break_en;
int dqsien_autok_dbg_mode_en;
/* ============================= */
/* >>>>>>>>>> RDDQC part begin >>>>>> */
/*
* 0: does not run rddq calibration
* 1: run rddq calibration
*/
int rddqc;
int low_byte_invert_golden;
int upper_byte_invert_golden;
int mr_dq_a_golden;
int mr_dq_b_golden;
int lp5_mr20_6_golden;
int lp5_mr20_7_golden;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run txperbit calibration
* 1: run txperbit calibration
*/
int tx_perbit;
/*
* 0: does not run txperbit auto calibration
* 1: run txperbit auto calibration
*/
int tx_auto_cal;
int tx_atk_pass_pi_thrd;
int tx_atk_early_break;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run rxperbit calibration
* 1: run rxperbit calibration
*/
int rx_perbit;
/*
* 0: does not run rxperbit auto calibration
* 1: run rxperbit auto calibration
*/
int rx_auto_cal;
int rx_atk_cal_step;
int rx_atk_cal_out_dbg_en;
int rx_atk_cal_out_dbg_sel;
/* ============================= */
} cal_sv_rand_args_t;
void set_psra(cal_sv_rand_args_t *psra);
cal_sv_rand_args_t *get_psra(void);
void print_sv_args(cal_sv_rand_args_t *psra);
u8 valid_magic(cal_sv_rand_args_t *psra);
void set_type_freq_by_svargs(DRAMC_CTX_T *p,
cal_sv_rand_args_t *psra);
#endif /* __SV_C_DATA_TRAFFIC_H */

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src/vendorcode/mediatek/mt8195/include/x_hal_io.h Normal file
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/*----------------------------------------------------------------------------*
* Copyright Statement: *
* *
* This software/firmware and related documentation ("MediaTek Software") *
* are protected under international and related jurisdictions'copyright laws *
* as unpublished works. The information contained herein is confidential and *
* proprietary to MediaTek Inc. Without the prior written permission of *
* MediaTek Inc., any reproduction, modification, use or disclosure of *
* MediaTek Software, and information contained herein, in whole or in part, *
* shall be strictly prohibited. *
* MediaTek Inc. Copyright (C) 2010. All rights reserved. *
* *
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND *
* AGREES TO THE FOLLOWING: *
* *
* 1)Any and all intellectual property rights (including without *
* limitation, patent, copyright, and trade secrets) in and to this *
* Software/firmware and related documentation ("MediaTek Software") shall *
* remain the exclusive property of MediaTek Inc. Any and all intellectual *
* property rights (including without limitation, patent, copyright, and *
* trade secrets) in and to any modifications and derivatives to MediaTek *
* Software, whoever made, shall also remain the exclusive property of *
* MediaTek Inc. Nothing herein shall be construed as any transfer of any *
* title to any intellectual property right in MediaTek Software to Receiver. *
* *
* 2)This MediaTek Software Receiver received from MediaTek Inc. and/or its *
* representatives is provided to Receiver on an "AS IS" basis only. *
* MediaTek Inc. expressly disclaims all warranties, expressed or implied, *
* including but not limited to any implied warranties of merchantability, *
* non-infringement and fitness for a particular purpose and any warranties *
* arising out of course of performance, course of dealing or usage of trade. *
* MediaTek Inc. does not provide any warranty whatsoever with respect to the *
* software of any third party which may be used by, incorporated in, or *
* supplied with the MediaTek Software, and Receiver agrees to look only to *
* such third parties for any warranty claim relating thereto. Receiver *
* expressly acknowledges that it is Receiver's sole responsibility to obtain *
* from any third party all proper licenses contained in or delivered with *
* MediaTek Software. MediaTek is not responsible for any MediaTek Software *
* releases made to Receiver's specifications or to conform to a particular *
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* *
* 3)Receiver further acknowledge that Receiver may, either presently *
* and/or in the future, instruct MediaTek Inc. to assist it in the *
* development and the implementation, in accordance with Receiver's designs, *
* of certain softwares relating to Receiver's product(s) (the "Services"). *
* Except as may be otherwise agreed to in writing, no warranties of any *
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* that testing is important and it is solely responsible for fully testing *
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* event of a conflict in the terms in any agreements entered into between *
* the parties. *
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* 4)Receiver's sole and exclusive remedy and MediaTek Inc.'s entire and *
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* 5)The transaction contemplated hereunder shall be construed in *
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*---------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
*
* Description:
*
*---------------------------------------------------------------------------*/
//vIO32WriteFldMulti
//vIO32WriteFldMulti_All
#ifndef X_HAL_IO_H
#define X_HAL_IO_H
#include "dramc_pi_api.h"
//===========================================================================
#define REG_ACCESS_NAO_DGB 0
#define REG_ACCESS_PORTING_DGB 0
#define REG_SHUFFLE_REG_CHECK 0
// field access macro-----------------------------------------------------------
/* field macros */
#define Fld(wid, shft) (((U32)wid << 16) | (shft << 8))
#define Fld_wid(fld) ((UINT8)((fld) >> 16))
#define Fld_shft(fld) ((UINT8)((fld) >> 8))
#define Fld_ac(fld) (UINT8)(fld)
/* access method*/
#define AC_FULLB0 1
#define AC_FULLB1 2
#define AC_FULLB2 3
#define AC_FULLB3 4
#define AC_FULLW10 5
#define AC_FULLW21 6
#define AC_FULLW32 7
#define AC_FULLDW 8
#define AC_MSKB0 11
#define AC_MSKB1 12
#define AC_MSKB2 13
#define AC_MSKB3 14
#define AC_MSKW10 15
#define AC_MSKW21 16
#define AC_MSKW32 17
#define AC_MSKDW 18
#define Fld2Msk32(fld) /*lint -save -e504 */ (((U32)0xffffffff>>(32-Fld_wid(fld)))<<Fld_shft(fld)) /*lint -restore */
#define P_Fld(val, fld) ( upk > 0 ? Fld2Msk32(fld): (((UINT32)(val) & ((1 << Fld_wid(fld)) - 1)) << Fld_shft(fld)))
extern U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr);
extern void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value);
extern void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32);
// =========================
// public Macro for general use.
//==========================
#define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32)
#define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32)
#define vIO32Write4B_All(reg32, val32) vIO32Write4B_All2(p, reg32, val32)
#define vIO32Write4BMsk(reg32, val32, msk32) vIO32Write4BMsk2(p, reg32, val32, msk32)
#define vIO32Write4BMsk_All(reg32, val32, msk32) vIO32Write4BMsk_All2(p, reg32, val32, msk32)
#define u4IO32ReadFldAlign(reg32, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
((u4IO32Read4B(reg32) & Fld2Msk32(fld)) >> Fld_shft(fld))
#define vIO32WriteFldAlign(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
(vIO32Write4BMsk((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
#define vIO32WriteFldMulti(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
{ \
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \
} \
}/*lint -restore */
//=========================
// Public Macro for write all-dramC or all-PHY registers
//=========================
#define vIO32WriteFldAlign_All(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
(vIO32Write4BMsk_All((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
#define vIO32WriteFldMulti_All(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
{ \
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \
} \
}/*lint -restore */
#ifdef __DPM__
#include "x_hal_io_dpm.h"
#endif
#endif // X_HAL_IO_H