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chromeos mainboards: remove chromeos.asl

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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin
2016-07-25 21:31:41 -05:00
committed by Duncan Laurie
parent 212820c8d7
commit b0f81518b5
126 changed files with 514 additions and 675 deletions
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19
src/mainboard/google/link/acpi/chromeos.asl
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@@ -1,19 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name(OIPG, Package() {
Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button
Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
})

11
src/mainboard/google/link/chromeos.c
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@@ -22,6 +22,7 @@
#include <southbridge/intel/common/gpio.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -107,3 +108,13 @@ int get_recovery_mode_switch(void)
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

1
src/mainboard/google/link/dsdt.asl
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@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
#include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */

2
src/mainboard/google/link/mainboard.c
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@@ -36,6 +36,7 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* placeholder for evenual link post. Not sure what we'll
* do but it will look nice
@@ -199,6 +200,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);