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chromeos mainboards: remove chromeos.asl

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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin
2016-07-25 21:31:41 -05:00
committed by Duncan Laurie
parent 212820c8d7
commit b0f81518b5
126 changed files with 514 additions and 675 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/mainboard/samsung/lumpy/acpi/chromeos.asl
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@@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name(OIPG, Package() {
Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
})

12
src/mainboard/samsung/lumpy/chromeos.c
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@@ -21,6 +21,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
@@ -135,3 +136,14 @@ void init_bootmode_straps(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

1
src/mainboard/samsung/lumpy/dsdt.asl
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@@ -52,7 +52,6 @@ DefinitionBlock(
}
}
#include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */

2
src/mainboard/samsung/lumpy/mainboard.c
View File

@@ -31,6 +31,7 @@
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -98,6 +99,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = lumpy_onboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

20
src/mainboard/samsung/stumpy/acpi/chromeos.asl
View File

@@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name(OIPG, Package() {
Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
})

12
src/mainboard/samsung/stumpy/chromeos.c
View File

@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
@@ -132,3 +133,14 @@ void init_bootmode_straps(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

1
src/mainboard/samsung/stumpy/dsdt.asl
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@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
#include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */

2
src/mainboard/samsung/stumpy/mainboard.c
View File

@@ -28,12 +28,14 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}