soc/intel/common: Add funtion to modify PAT & NXE bit

Add function to modify NXE bit & PAT.

BUG=None
BRANCH=None
TEST=Make sure build for Glkrvp is successful.

Change-Id: I265d6d5ca538496934a375eb8d99d52879522051
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25480
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cpu/cpulib.c

@@ -314,3 +314,23 @@ void mca_configure(void)
 			(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
 	}
 }
+
+void set_nxe(uint8_t enable)
+{
+	msr_t msr = rdmsr(IA32_EFER);
+
+	if (enable)
+		msr.lo |= EFER_NXE;
+	else
+		msr.lo &= ~EFER_NXE;
+
+	wrmsr(IA32_EFER, msr);
+}
+
+void set_pat(uint64_t pat)
+{
+	msr_t msr;
+	msr.lo = pat;
+	msr.hi = pat >> 32;
+	wrmsr(MSR_IA32_PAT, msr);
+}

src/soc/intel/common/block/include/intelblocks/cpulib.h

@@ -159,4 +159,9 @@ uint32_t cpu_get_max_turbo_ratio(void);
 /* Configure Machine Check Architecture support */
 void mca_configure(void);
 
+/* Set/Clear NXE bit in IA32_EFER MSR */
+void set_nxe(uint8_t enable);
+
+/* Set PAT MSR */
+void set_pat(uint64_t pat);
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -72,6 +72,7 @@
 #define  PRMRR_PHYS_MASK_LOCK		(1 << 10)
 #define  PRMRR_PHYS_MASK_VALID		(1 << 11)
 #define MSR_POWER_CTL			0x1fc
+#define MSR_IA32_PAT			0x277
 #define MSR_EVICT_CTL			0x2e0
 #define MSR_SGX_OWNEREPOCH0		0x300
 #define MSR_SGX_OWNEREPOCH1		0x301
@@ -142,4 +143,13 @@
 #define SGX_RESOURCE_MASK_LO	(0xfffff000UL)
 #define SGX_RESOURCE_MASK_HI	(0xfffffUL)
 
+/* Intel SDM: Table 2-1
+ * IA-32 architectural MSR: Extended Feature Enable Register
+ */
+#define IA32_EFER	0xC0000080
+#define  EFER_NXE	(1 << 11)
+#define  EFER_LMA	(1 << 10)
+#define  EFER_LME	(1 << 8)
+#define  EFER_SCE	(1 << 0)
+
 #endif	/* SOC_INTEL_COMMON_MSR_H */