sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

skylake: Rework microcode include path

Browse Source 
Remove the microcode include path config options and include
the mainboard blob directory by default.

BUG=chrome-os-partner:42109
BRANCH=none
TEST=emerge-glados coreboot
CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922

Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448
Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285150
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11053
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie
2015-07-13 10:44:05 -07:00
committed by Patrick Georgi
parent ef0158ec90
commit b10f42bb0a
4 changed files with 1 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/intel/skylake/Kconfig
View File

@@ -96,11 +96,6 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
config EXTRA_MICROCODE_INCLUDE_PATH
string "Include path for extra microcode patches."
help
The path to any extra microcode patches from other sources.
config HAVE_IFD_BIN
bool "Use Intel Firmware Descriptor from existing binary"
default n
@@ -166,10 +161,6 @@ config ME_BIN_PATH
depends on HAVE_ME_BIN
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config MICROCODE_INCLUDE_PATH
string
default "src/soc/intel/skylake/microcode"
config MMCONF_BASE_ADDRESS
hex "MMIO Base Address"
default 0xe0000000