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I82801JX: Add IS_ENABLED around config options

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This chipset was just added and had a few places that needed to be
fixed.

Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth 2017-07-21 10:23:57 -06:00
parent 837afb0938
commit b137c13e57
4 changed files with 5 additions and 5 deletions
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2
src/cpu/x86/smm/smmrelocate.S
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@ -29,7 +29,7 @@
#include "../../../soc/intel/sch/sch.h" #include "../../../soc/intel/sch/sch.h"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
#include "../../../southbridge/intel/i82801ix/i82801ix.h" #include "../../../southbridge/intel/i82801ix/i82801ix.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801JX #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)
#include "../../../southbridge/intel/i82801jx/i82801jx.h" #include "../../../southbridge/intel/i82801jx/i82801jx.h"
#else #else

2
src/southbridge/intel/i82801jx/acpi/sleepstates.asl
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@ -15,7 +15,7 @@
*/ */
Name(\_S0, Package(){0x0,0x0,0x0,0x0}) Name(\_S0, Package(){0x0,0x0,0x0,0x0})
#if !CONFIG_HAVE_ACPI_RESUME #if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0}) Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else #else
Name(\_S3, Package(){0x5,0x0,0x0,0x0}) Name(\_S3, Package(){0x5,0x0,0x0,0x0})

2
src/southbridge/intel/i82801jx/i82801jx.c
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@ -222,7 +222,7 @@ static void i82801jx_init(void *chip_info)
i82801jx_hide_functions(); i82801jx_hide_functions();
/* Reset watchdog timer. */ /* Reset watchdog timer. */
#if !CONFIG_HAVE_SMI_HANDLER #if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif #endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */

4
src/southbridge/intel/i82801jx/lpc.c
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@ -369,7 +369,7 @@ static void enable_clock_gating(void)
RCBA32(0x38c0) |= 7; RCBA32(0x38c0) |= 7;
} }
#if CONFIG_HAVE_SMI_HANDLER #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801jx_lock_smm(struct device *dev) static void i82801jx_lock_smm(struct device *dev)
{ {
#if TEST_SMM_FLASH_LOCKDOWN #if TEST_SMM_FLASH_LOCKDOWN
@ -464,7 +464,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */ /* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1); i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801jx_lock_smm(dev); i82801jx_lock_smm(dev);
#endif #endif
} }