sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/braswell: Get rid of device_t

Browse Source 
Use of device_t has been abandoned in ramstage.

Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS
2018-05-24 22:29:44 +02:00
committed by Kyösti Mälkki
parent 15a487a576
commit b13fac37eb
17 changed files with 62 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/braswell/acpi.c
View File

@ -420,7 +420,7 @@ static void generate_p_state_entries(int core, int cores_per_package)
acpigen_pop_len(); acpigen_pop_len();
} }
void generate_cpu_entries(device_t device) void generate_cpu_entries(struct device *device)
{ {
int core; int core;
int pcontrol_blk = get_pmbase(), plen = 6; int pcontrol_blk = get_pmbase(), plen = 6;
@ -482,7 +482,7 @@ static int update_igd_opregion(igd_opregion_t *opregion)
return 0; return 0;
} }
unsigned long southcluster_write_acpi_tables(device_t device, unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current, unsigned long current,
struct acpi_rsdp *rsdp) struct acpi_rsdp *rsdp)
{ {
@ -524,7 +524,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
return current; return current;
} }
void southcluster_inject_dsdt(device_t device) void southcluster_inject_dsdt(struct device *device)
{ {
global_nvs_t *gnvs; global_nvs_t *gnvs;

12
src/soc/intel/braswell/chip.c
View File

@ -23,7 +23,7 @@
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -38,7 +38,7 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
}; };
static void cpu_bus_noop(device_t dev) { } static void cpu_bus_noop(struct device *dev) { }
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop, .read_resources = cpu_bus_noop,
@ -48,7 +48,7 @@ static struct device_operations cpu_bus_ops = {
}; };
static void enable_dev(device_t dev) static void enable_dev(struct device *dev)
{ {
printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",
__FILE__, __func__, __FILE__, __func__,
@ -87,7 +87,7 @@ __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params)
void soc_silicon_init_params(SILICON_INIT_UPD *params) void soc_silicon_init_params(SILICON_INIT_UPD *params)
{ {
device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct soc_intel_braswell_config *config; struct soc_intel_braswell_config *config;
if (!dev) { if (!dev) {
@ -382,7 +382,7 @@ struct chip_operations soc_intel_braswell_ops = {
.init = soc_init, .init = soc_init,
}; };
static void pci_set_subsystem(device_t dev, unsigned int vendor, static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device) unsigned int device)
{ {
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
@ -407,7 +407,7 @@ struct pci_operations soc_pci_ops = {
**/ **/
int SocStepping(void) int SocStepping(void)
{ {
device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
u8 revid = pci_read_config8(dev, 0x8); u8 revid = pci_read_config8(dev, 0x8);
switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {

4
src/soc/intel/braswell/cpu.c
View File

@ -45,7 +45,7 @@ static const struct reg_script core_msr_script[] = {
REG_SCRIPT_END REG_SCRIPT_END
}; };
static void soc_core_init(device_t cpu) static void soc_core_init(struct device *cpu)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(cpu)); __FILE__, __func__, dev_name(cpu));
@ -215,7 +215,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = southcluster_smm_enable_smi, .post_mp_init = southcluster_smm_enable_smi,
}; };
void soc_init_cpus(device_t dev) void soc_init_cpus(struct device *dev)
{ {
struct bus *cpu_bus = dev->link_list; struct bus *cpu_bus = dev->link_list;

2
src/soc/intel/braswell/emmc.c
View File

@ -32,7 +32,7 @@ static const struct reg_script emmc_ops[] = {
REG_SCRIPT_END, REG_SCRIPT_END,
}; };
static void emmc_init(device_t dev) static void emmc_init(struct device *dev)
{ {
struct soc_intel_braswell_config *config = dev->chip_info; struct soc_intel_braswell_config *config = dev->chip_info;

9
src/soc/intel/braswell/gfx.c
View File

@ -41,12 +41,13 @@ static const struct reg_script gfx_post_vbios_script[] = {
REG_SCRIPT_END REG_SCRIPT_END
}; };
static inline void gfx_run_script(device_t dev, const struct reg_script *ops) static inline void gfx_run_script(struct device *dev,
const struct reg_script *ops)
{ {
reg_script_run_on_dev(dev, ops); reg_script_run_on_dev(dev, ops);
} }
static void gfx_pre_vbios_init(device_t dev) static void gfx_pre_vbios_init(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -54,7 +55,7 @@ static void gfx_pre_vbios_init(device_t dev)
gfx_run_script(dev, gpu_pre_vbios_script); gfx_run_script(dev, gpu_pre_vbios_script);
} }
static void gfx_post_vbios_init(device_t dev) static void gfx_post_vbios_init(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -62,7 +63,7 @@ static void gfx_post_vbios_init(device_t dev)
gfx_run_script(dev, gfx_post_vbios_script); gfx_run_script(dev, gfx_post_vbios_script);
} }
static void gfx_init(device_t dev) static void gfx_init(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));

4
src/soc/intel/braswell/include/soc/acpi.h
View File

@ -24,8 +24,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t *fadt); void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs); void acpi_init_gnvs(global_nvs_t *gnvs);
void southcluster_inject_dsdt(device_t device); void southcluster_inject_dsdt(struct device *device);
unsigned long southcluster_write_acpi_tables(device_t device, unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current, struct acpi_rsdp *rsdp); unsigned long current, struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */ #endif /* _SOC_ACPI_H_ */

6
src/soc/intel/braswell/include/soc/ramstage.h
View File

@ -96,10 +96,10 @@ enum {
* initialization, but it's after console and cbmem has been reinitialized. * initialization, but it's after console and cbmem has been reinitialized.
*/ */
void soc_init_pre_device(struct soc_intel_braswell_config *config); void soc_init_pre_device(struct soc_intel_braswell_config *config);
void soc_init_cpus(device_t dev); void soc_init_cpus(struct device *dev);
void set_max_freq(void); void set_max_freq(void);
void southcluster_enable_dev(device_t dev); void southcluster_enable_dev(struct device *dev);
void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
int SocStepping(void); int SocStepping(void);
void board_silicon_USB2_override(SILICON_INIT_UPD *params); void board_silicon_USB2_override(SILICON_INIT_UPD *params);

15
src/soc/intel/braswell/lpe.c
View File

@ -44,7 +44,8 @@
#define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
static void assign_device_nvs(device_t dev, u32 *field, unsigned int index) static void assign_device_nvs(struct device *dev, u32 *field,
unsigned int index)
{ {
struct resource *res; struct resource *res;
@ -53,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned int index)
*field = res->base; *field = res->base;
} }
static void lpe_enable_acpi_mode(device_t dev) static void lpe_enable_acpi_mode(struct device *dev)
{ {
static const struct reg_script ops[] = { static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */ /* Disable PCI interrupt, enable Memory and Bus Master */
@ -87,7 +88,7 @@ static void lpe_enable_acpi_mode(device_t dev)
reg_script_run_on_dev(dev, ops); reg_script_run_on_dev(dev, ops);
} }
static void setup_codec_clock(device_t dev) static void setup_codec_clock(struct device *dev)
{ {
uint32_t reg; uint32_t reg;
u32 *clk_reg; u32 *clk_reg;
@ -123,7 +124,7 @@ static void setup_codec_clock(device_t dev)
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
} }
static void lpe_stash_firmware_info(device_t dev) static void lpe_stash_firmware_info(struct device *dev)
{ {
struct resource *res; struct resource *res;
struct resource *mmio; struct resource *mmio;
@ -148,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev)
} }
static void lpe_init(device_t dev) static void lpe_init(struct device *dev)
{ {
struct soc_intel_braswell_config *config = dev->chip_info; struct soc_intel_braswell_config *config = dev->chip_info;
@ -162,7 +163,7 @@ static void lpe_init(device_t dev)
lpe_enable_acpi_mode(dev); lpe_enable_acpi_mode(dev);
} }
static void lpe_read_resources(device_t dev) static void lpe_read_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
@ -184,7 +185,7 @@ static void lpe_read_resources(device_t dev)
FIRMWARE_PHYS_LENGTH >> 10); FIRMWARE_PHYS_LENGTH >> 10);
} }
static void lpe_set_resources(device_t dev) static void lpe_set_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;

9
src/soc/intel/braswell/lpss.c
View File

@ -30,7 +30,8 @@
#include "chip.h" #include "chip.h"
static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) static void dev_enable_acpi_mode(struct device *dev,
int iosf_reg, int nvs_index)
{ {
struct reg_script ops[] = { struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */ /* Disable PCI interrupt, enable Memory and Bus Master */
@ -67,7 +68,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
reg_script_run_on_dev(dev, ops); reg_script_run_on_dev(dev, ops);
} }
static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{ {
*iosf_reg = -1; *iosf_reg = -1;
*nvs_index = -1; *nvs_index = -1;
@ -110,7 +111,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
} }
} }
static void i2c_disable_resets(device_t dev) static void i2c_disable_resets(struct device *dev)
{ {
/* Release the I2C devices from reset. */ /* Release the I2C devices from reset. */
static const struct reg_script ops[] = { static const struct reg_script ops[] = {
@ -137,7 +138,7 @@ static void i2c_disable_resets(device_t dev)
} }
} }
static void lpss_init(device_t dev) static void lpss_init(struct device *dev)
{ {
struct soc_intel_braswell_config *config = dev->chip_info; struct soc_intel_braswell_config *config = dev->chip_info;
int iosf_reg, nvs_index; int iosf_reg, nvs_index;

2
src/soc/intel/braswell/northcluster.c
View File

@ -81,7 +81,7 @@ uint32_t nc_read_top_of_low_memory(void)
return tolm; return tolm;
} }
static void nc_read_resources(device_t dev) static void nc_read_resources(struct device *dev)
{ {
unsigned long mmconf; unsigned long mmconf;
unsigned long bmbound_k; unsigned long bmbound_k;

16
src/soc/intel/braswell/pcie.c
View File

@ -29,17 +29,17 @@
static int pll_en_off; static int pll_en_off;
static uint32_t strpfusecfg; static uint32_t strpfusecfg;
static inline int root_port_offset(device_t dev) static inline int root_port_offset(struct device *dev)
{ {
return PCI_FUNC(dev->path.pci.devfn); return PCI_FUNC(dev->path.pci.devfn);
} }
static inline int is_first_port(device_t dev) static inline int is_first_port(struct device *dev)
{ {
return root_port_offset(dev) == PCIE_PORT1_FUNC; return root_port_offset(dev) == PCIE_PORT1_FUNC;
} }
static void pcie_init(device_t dev) static void pcie_init(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -52,7 +52,7 @@ static const struct reg_script no_dev_behind_port[] = {
REG_SCRIPT_END, REG_SCRIPT_END,
}; };
static void check_port_enabled(device_t dev) static void check_port_enabled(struct device *dev)
{ {
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
@ -81,10 +81,10 @@ static void check_port_enabled(device_t dev)
} }
} }
static void check_device_present(device_t dev) static void check_device_present(struct device *dev)
{ {
/* port1_dev will store the dev struct pointer of the PORT1 */ /* port1_dev will store the dev struct pointer of the PORT1 */
static device_t port1_dev; static struct device *port1_dev;
/* /*
* The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW.
@ -135,7 +135,7 @@ static void check_device_present(device_t dev)
} }
} }
static void pcie_enable(device_t dev) static void pcie_enable(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -159,7 +159,7 @@ static void pcie_enable(device_t dev)
southcluster_enable_dev(dev); southcluster_enable_dev(dev);
} }
static void pcie_root_set_subsystem(device_t dev, unsigned int vid, static void pcie_root_set_subsystem(struct device *dev, unsigned int vid,
unsigned int did) unsigned int did)
{ {
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",

2
src/soc/intel/braswell/ramstage.c
View File

@ -78,7 +78,7 @@ static const char * const stepping_str[] = {
static void fill_in_pattrs(void) static void fill_in_pattrs(void)
{ {
device_t dev; struct device *dev;
msr_t msr; msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get(); struct pattrs *attrs = (struct pattrs *)pattrs_get();

2
src/soc/intel/braswell/sata.c
View File

@ -34,7 +34,7 @@ static void sata_init(struct device *dev)
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
} }
static void sata_enable(device_t dev) static void sata_enable(struct device *dev)
{ {
southcluster_enable_dev(dev); southcluster_enable_dev(dev);
} }

2
src/soc/intel/braswell/scc.c
View File

@ -24,7 +24,7 @@
#include <soc/nvs.h> #include <soc/nvs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{ {
struct resource *bar; struct resource *bar;
global_nvs_t *gnvs; global_nvs_t *gnvs;

2
src/soc/intel/braswell/sd.c
View File

@ -31,7 +31,7 @@
#define CAP_OVERRIDE_HIGH 0xa4 #define CAP_OVERRIDE_HIGH 0xa4
# define USE_CAP_OVERRIDES (1 << 31) # define USE_CAP_OVERRIDES (1 << 31)
static void sd_init(device_t dev) static void sd_init(struct device *dev)
{ {
struct soc_intel_braswell_config *config = dev->chip_info; struct soc_intel_braswell_config *config = dev->chip_info;

24
src/soc/intel/braswell/southcluster.c
View File

@ -53,14 +53,15 @@ static void enable_serirq_quiet_mode(void)
} }
static inline void static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{ {
printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",
__FILE__, __func__, dev_name(dev), addr, size); __FILE__, __func__, dev_name(dev), addr, size);
mmio_resource(dev, i, addr >> 10, size >> 10); mmio_resource(dev, i, addr >> 10, size >> 10);
} }
static void sc_add_mmio_resources(device_t dev) static void sc_add_mmio_resources(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -97,7 +98,8 @@ static inline int io_range_in_default(int base, int size)
* Note: this function assumes there is no overlap with the default LPC device's * Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/ */
static void sc_add_io_resource(device_t dev, int base, int size, int index) static void sc_add_io_resource(struct device *dev, int base, int size,
int index)
{ {
struct resource *res; struct resource *res;
@ -113,7 +115,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void sc_add_io_resources(device_t dev) static void sc_add_io_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;
@ -133,7 +135,7 @@ static void sc_add_io_resources(device_t dev)
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
} }
static void sc_read_resources(device_t dev) static void sc_read_resources(struct device *dev)
{ {
printk(BIOS_SPEW, "%s/%s ( %s )\n", printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev)); __FILE__, __func__, dev_name(dev));
@ -154,7 +156,7 @@ static void sc_rtc_init(void)
cmos_init(rtc_failure()); cmos_init(rtc_failure());
} }
static void sc_init(device_t dev) static void sc_init(struct device *dev)
{ {
int i; int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
@ -198,7 +200,7 @@ static void sc_init(device_t dev)
*/ */
/* Set bit in function disble register to hide this device. */ /* Set bit in function disble register to hide this device. */
static void sc_disable_devfn(device_t dev) static void sc_disable_devfn(struct device *dev)
{ {
void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
@ -287,7 +289,7 @@ static void sc_disable_devfn(device_t dev)
} }
} }
static inline void set_d3hot_bits(device_t dev, int offset) static inline void set_d3hot_bits(struct device *dev, int offset)
{ {
uint32_t reg8; uint32_t reg8;
@ -304,7 +306,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* cannot put HDA into D3Hot. Instead perform this workaround to make some of * cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. * the audio paths work for LPE audio.
*/ */
static void hda_work_around(device_t dev) static void hda_work_around(struct device *dev)
{ {
void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
@ -326,7 +328,7 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
} }
static int place_device_in_d3hot(device_t dev) static int place_device_in_d3hot(struct device *dev)
{ {
unsigned int offset; unsigned int offset;
@ -405,7 +407,7 @@ static int place_device_in_d3hot(device_t dev)
} }
/* Common PCI device function disable. */ /* Common PCI device function disable. */
void southcluster_enable_dev(device_t dev) void southcluster_enable_dev(struct device *dev)
{ {
uint32_t reg32; uint32_t reg32;

2
src/soc/intel/braswell/xhci.c
View File

@ -32,7 +32,7 @@
#include "chip.h" #include "chip.h"
static void xhci_init(device_t dev) static void xhci_init(struct device *dev)
{ {
struct soc_intel_braswell_config *config = dev->chip_info; struct soc_intel_braswell_config *config = dev->chip_info;