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Fix 'unsigned int' to bare use of 'unsigned'

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Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Subrata Banik
2019-03-15 22:20:41 +05:30
parent d0e218384f
commit b1434fce01
11 changed files with 127 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -43,7 +43,7 @@ static struct device *__f0_dev[FX_DEVS];
static struct device *__f1_dev[FX_DEVS];
static struct device *__f2_dev[FX_DEVS];
static struct device *__f4_dev[FX_DEVS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
struct dram_base_mask_t {
u32 base; //[47:27] at [28:8]
@ -129,7 +129,7 @@ static void get_fx_devs(void)
die("Cannot find 0:0x18.[0|1]\n");
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
@ -137,7 +137,7 @@ static u32 f1_read_config32(unsigned reg)
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -176,11 +176,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
static int reg_useable(unsigned reg, struct device *goal_dev,
unsigned goal_nodeid, unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
res = 0;
@ -206,7 +206,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev,
}
static struct resource *amdfam12_find_iopair(struct device *dev,
unsigned nodeid, unsigned link)
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 result, reg;
@ -324,7 +324,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
@ -378,7 +378,7 @@ static void set_resource(struct device *dev, struct resource *resource,
u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
unsigned int reg, link_num;
char buf[50];
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
@ -428,7 +428,7 @@ static void set_resource(struct device *dev, struct resource *resource,
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -461,7 +461,7 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
static void set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -488,7 +488,7 @@ static void set_resources(struct device *dev)
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
@ -500,7 +500,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
@ -622,7 +622,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, idx, basek, pre_sizek);

28
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -40,7 +40,7 @@ static struct device *__f0_dev[FX_DEVS];
static struct device *__f1_dev[FX_DEVS];
static struct device *__f2_dev[FX_DEVS];
static struct device *__f4_dev[FX_DEVS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
struct dram_base_mask_t {
@ -127,14 +127,14 @@ static void get_fx_devs(void)
}
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -169,11 +169,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
static int reg_useable(unsigned reg, struct device *goal_dev,
unsigned goal_nodeid, unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@ -197,7 +197,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev,
}
static struct resource *amdfam14_find_iopair(struct device *dev,
unsigned nodeid, unsigned link)
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 result, reg;
@ -314,7 +314,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
@ -365,7 +365,7 @@ static void set_resource(struct device *dev, struct resource *resource,
u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
unsigned int reg, link_num;
char buf[50];
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
@ -414,7 +414,7 @@ static void set_resource(struct device *dev, struct resource *resource,
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -448,7 +448,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
static void nb_set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -475,7 +475,7 @@ static void nb_set_resources(struct device *dev)
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
@ -487,7 +487,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base & 0x30);
@ -600,7 +600,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, idx, basek,

41
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -45,13 +45,13 @@ typedef struct dram_base_mask {
u32 mask; //[47:27] at [28:8] and enable at bit 0
} dram_base_mask_t;
static unsigned node_nums;
static unsigned sblink;
static unsigned int node_nums;
static unsigned int sblink;
static struct device *__f0_dev[MAX_NODE_NUMS];
static struct device *__f1_dev[MAX_NODE_NUMS];
static struct device *__f2_dev[MAX_NODE_NUMS];
static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
@ -120,14 +120,14 @@ static void get_fx_devs(void)
printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -165,11 +165,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
* @retval 0 resource exists, not usable
* @retval 1 resource exist, resource has been allocated before
*/
static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@ -193,7 +193,8 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
return result;
}
static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
static struct resource *amdfam15_find_iopair(struct device *dev,
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 free_reg, reg;
@ -311,7 +312,7 @@ static void nb_read_resources(struct device *dev)
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
unsigned int reg, link_num;
char buf[50];
/* Make certain the resource has actually been set */
@ -359,7 +360,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
* but it is too difficult to deal with the resource allocation magic.
*/
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -389,7 +390,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
static void nb_set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -572,7 +573,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = {
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
/* Find the already assigned resource pairs */
get_fx_devs();
@ -582,7 +583,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
@ -609,7 +610,7 @@ static void domain_read_resources(struct device *dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@ -724,7 +725,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
@ -771,7 +772,7 @@ static void sysconf_init(struct device *dev) // first node
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
}
static void add_more_links(struct device *dev, unsigned total_links)
static void add_more_links(struct device *dev, unsigned int total_links)
{
struct bus *link, *last = NULL;
int link_num;
@ -814,8 +815,8 @@ static void cpu_bus_scan(struct device *dev)
int i,j;
int coreid_bits;
int core_max = 0;
unsigned ApicIdCoreIdSize;
unsigned core_nums;
unsigned int ApicIdCoreIdSize;
unsigned int core_nums;
int siblings = 0;
unsigned int family;
@ -841,7 +842,7 @@ static void cpu_bus_scan(struct device *dev)
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
struct device *cdb_dev;
unsigned devn;
unsigned int devn;
struct bus *pbus;
devn = DEV_CDB + i;

42
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -44,13 +44,13 @@ typedef struct dram_base_mask {
u32 mask; //[47:27] at [28:8] and enable at bit 0
} dram_base_mask_t;
static unsigned node_nums;
static unsigned sblink;
static unsigned int node_nums;
static unsigned int sblink;
static struct device *__f0_dev[MAX_NODE_NUMS];
static struct device *__f1_dev[MAX_NODE_NUMS];
static struct device *__f2_dev[MAX_NODE_NUMS];
static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
@ -119,14 +119,14 @@ static void get_fx_devs(void)
printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -164,11 +164,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
* @retval 0 resource exists, not usable
* @retval 1 resource exist, resource has been allocated before
*/
static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@ -192,7 +192,8 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
return result;
}
static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
static struct resource *amdfam16_find_iopair(struct device *dev,
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 free_reg, reg;
@ -310,7 +311,7 @@ static void read_resources(struct device *dev)
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
unsigned int reg, link_num;
char buf[50];
/* Make certain the resource has actually been set */
@ -358,7 +359,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
* but it is too difficult to deal with the resource allocation magic.
*/
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -388,7 +389,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
static void set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -409,7 +410,6 @@ static void set_resources(struct device *dev)
}
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
{
void *addr, *current;
@ -589,7 +589,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = {
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
/* Find the already assigned resource pairs */
get_fx_devs();
@ -599,7 +599,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
@ -626,7 +626,7 @@ static void domain_read_resources(struct device *dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@ -742,7 +742,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
@ -798,7 +798,7 @@ static void sysconf_init(struct device *dev) // first node
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
}
static void add_more_links(struct device *dev, unsigned total_links)
static void add_more_links(struct device *dev, unsigned int total_links)
{
struct bus *link, *last = NULL;
int link_num;
@ -841,8 +841,8 @@ static void cpu_bus_scan(struct device *dev)
int i,j;
int coreid_bits;
int core_max = 0;
unsigned ApicIdCoreIdSize;
unsigned core_nums;
unsigned int ApicIdCoreIdSize;
unsigned int core_nums;
int siblings = 0;
unsigned int family;
@ -868,7 +868,7 @@ static void cpu_bus_scan(struct device *dev)
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
struct device *cdb_dev;
unsigned devn;
unsigned int devn;
struct bus *pbus;
devn = DEV_CDB + i;

6
src/northbridge/amd/amdk8/reset_test.c
View File

@ -16,7 +16,7 @@
#include <cpu/x86/lapic.h>
#include "amdk8.h"
static inline int cpu_init_detected(unsigned nodeid)
static inline int cpu_init_detected(unsigned int nodeid)
{
u32 htic;
pci_devfn_t dev;
@ -61,7 +61,7 @@ void set_bios_reset(void)
pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
static unsigned node_link_to_bus(unsigned node, unsigned link)
static unsigned int node_link_to_bus(unsigned int node, unsigned int link)
{
u8 reg;
@ -88,7 +88,7 @@ unsigned int get_sblk(void)
return ((reg>>8) & 3);
}
unsigned int get_sbbusn(unsigned sblk)
unsigned int get_sbbusn(unsigned int sblk)
{
return node_link_to_bus(0, sblk);
}

37
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -48,13 +48,13 @@ typedef struct dram_base_mask {
u32 mask; //[47:27] at [28:8] and enable at bit 0
} dram_base_mask_t;
static unsigned node_nums;
static unsigned sblink;
static unsigned int node_nums;
static unsigned int sblink;
static struct device *__f0_dev[MAX_NODE_NUMS];
static struct device *__f1_dev[MAX_NODE_NUMS];
static struct device *__f2_dev[MAX_NODE_NUMS];
static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
@ -123,14 +123,14 @@ static void get_fx_devs(void)
printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -168,11 +168,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
* @retval 0 resource exists, but is not usable
* @retval 1 resource exists, but has been allocated before
*/
static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@ -196,7 +196,8 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
return result;
}
static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
static struct resource *amdfam15_find_iopair(struct device *dev,
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 free_reg, reg;
@ -362,7 +363,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
* but it is too difficult to deal with the resource allocation magic.
*/
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -394,7 +395,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
static void set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -573,7 +574,7 @@ struct chip_operations northbridge_amd_pi_00630F01_ops = {
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
/* Find the already assigned resource pairs */
get_fx_devs();
@ -583,7 +584,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
@ -625,7 +626,7 @@ static void domain_enable_resources(struct device *dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@ -742,7 +743,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
@ -833,8 +834,8 @@ static void cpu_bus_scan(struct device *dev)
int i,j;
int coreid_bits;
int core_max = 0;
unsigned ApicIdCoreIdSize;
unsigned core_nums;
unsigned int ApicIdCoreIdSize;
unsigned int core_nums;
int siblings = 0;
unsigned int family;
u32 modules = 0;
@ -876,7 +877,7 @@ static void cpu_bus_scan(struct device *dev)
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
struct device *cdb_dev;
unsigned devn;
unsigned int devn;
struct bus *pbus;
devn = DEV_CDB + i;

8
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -573,7 +573,7 @@ struct chip_operations northbridge_amd_pi_00660F01_ops = {
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
/* Find the already assigned resource pairs */
get_fx_devs();
@ -583,7 +583,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base & 0x30);
@ -621,7 +621,7 @@ static void domain_enable_resources(struct device *dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@ -738,7 +738,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);

41
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -49,13 +49,13 @@ typedef struct dram_base_mask {
u32 mask; //[47:27] at [28:8] and enable at bit 0
} dram_base_mask_t;
static unsigned node_nums;
static unsigned sblink;
static unsigned int node_nums;
static unsigned int sblink;
static struct device *__f0_dev[MAX_NODE_NUMS];
static struct device *__f1_dev[MAX_NODE_NUMS];
static struct device *__f2_dev[MAX_NODE_NUMS];
static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static unsigned int fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
@ -124,14 +124,14 @@ static void get_fx_devs(void)
printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
static u32 f1_read_config32(unsigned int reg)
{
if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, u32 value)
static void f1_write_config32(unsigned int reg, u32 value)
{
int i;
if (fx_devs == 0)
@ -169,11 +169,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
* @retval 0 resource exists, not usable
* @retval 1 resource exist, resource has been allocated before
*/
static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
static int reg_useable(unsigned int reg, struct device *goal_dev,
unsigned int goal_nodeid, unsigned int goal_link)
{
struct resource *res;
unsigned nodeid, link = 0;
unsigned int nodeid, link = 0;
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@ -197,7 +197,8 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node
return result;
}
static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
static struct resource *amdfam16_find_iopair(struct device *dev,
unsigned int nodeid, unsigned int link)
{
struct resource *resource;
u32 free_reg, reg;
@ -315,7 +316,7 @@ static void read_resources(struct device *dev)
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
unsigned int reg, link_num;
char buf[50];
/* Make certain the resource has actually been set */
@ -363,7 +364,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node
* but it is too difficult to deal with the resource allocation magic.
*/
static void create_vga_resource(struct device *dev, unsigned nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
{
struct bus *link;
@ -393,7 +394,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid)
static void set_resources(struct device *dev)
{
unsigned nodeid;
unsigned int nodeid;
struct bus *bus;
struct resource *res;
@ -807,7 +808,7 @@ struct chip_operations northbridge_amd_pi_00730F01_ops = {
static void domain_read_resources(struct device *dev)
{
unsigned reg;
unsigned int reg;
/* Find the already assigned resource pairs */
get_fx_devs();
@ -817,7 +818,7 @@ static void domain_read_resources(struct device *dev)
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
unsigned int nodeid, reg_link;
struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
@ -854,7 +855,7 @@ static void domain_enable_resources(struct device *dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
unsigned int hole_startk;
int node_id;
};
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@ -971,7 +972,7 @@ static void domain_set_resources(struct device *dev)
/* split the region to accommodate pci memory space */
if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
@ -1028,7 +1029,7 @@ static void sysconf_init(struct device *dev) // first node
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
}
static void add_more_links(struct device *dev, unsigned total_links)
static void add_more_links(struct device *dev, unsigned int total_links)
{
struct bus *link, *last = NULL;
int link_num;
@ -1071,8 +1072,8 @@ static void cpu_bus_scan(struct device *dev)
int i,j;
int coreid_bits;
int core_max = 0;
unsigned ApicIdCoreIdSize;
unsigned core_nums;
unsigned int ApicIdCoreIdSize;
unsigned int core_nums;
int siblings = 0;
unsigned int family;
u32 modules = 0;
@ -1114,7 +1115,7 @@ static void cpu_bus_scan(struct device *dev)
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
struct device *cdb_dev;
unsigned devn;
unsigned int devn;
struct bus *pbus;
devn = DEV_CDB + i;

2
src/northbridge/intel/sandybridge/gma.c
View File

@ -300,7 +300,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
#define GTT_RETRY 1000
int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
unsigned int try = GTT_RETRY;
u32 data;
while (try--) {

16
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -1577,8 +1577,8 @@ static int get_precedening_channels(ramctr_timing * ctrl, int target_channel)
static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
{
unsigned j;
unsigned channel_offset =
unsigned int j;
unsigned int channel_offset =
get_precedening_channels(ctrl, channel) * 0x40;
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
@ -1595,10 +1595,10 @@ static int num_of_channels(const ramctr_timing * ctrl)
static void fill_pattern1(ramctr_timing * ctrl, int channel)
{
unsigned j;
unsigned channel_offset =
unsigned int j;
unsigned int channel_offset =
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
unsigned int channel_step = 0x40 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
for (j = 0; j < 16; j++)
@ -2125,10 +2125,10 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
{
unsigned i, j;
unsigned channel_offset =
unsigned int i, j;
unsigned int channel_offset =
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
unsigned int channel_step = 0x40 * num_of_channels(ctrl);
if (patno) {
u8 base8 = 0x80 >> ((patno - 1) % 8);

2
src/soc/intel/common/block/pcie/pcie.c
View File

@ -73,7 +73,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
}
static void pcie_dev_set_subsystem(struct device *dev,
unsigned vendor, unsigned device)
unsigned int vendor, unsigned int device)
{
pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));