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mb/google/nissa: Don't put WLAN into D3cold

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On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.

BUG=b:233325709
TEST=Wake-on-WLAN works on nereid

Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Reka Norman
2022-07-07 14:49:58 +10:00
committed by Felix Held
parent 6297df85d6
commit b146c7a7c0
2 changed files with 0 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/nereid/overridetree.cb
View File

@@ -210,12 +210,6 @@ chip soc/intel/alderlake
register "wake" = "GPE0_DW1_03" register "wake" = "GPE0_DW1_03"
device pci 00.0 on end device pci 00.0 on end
end end
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end end
device ref pch_espi on device ref pch_espi on
chip ec/google/chromeec chip ec/google/chromeec

6
src/mainboard/google/brya/variants/xivu/overridetree.cb
View File

@@ -188,12 +188,6 @@ chip soc/intel/alderlake
register "wake" = "GPE0_DW1_03" register "wake" = "GPE0_DW1_03"
device pci 00.0 on end device pci 00.0 on end
end end
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end end
device ref pch_espi on device ref pch_espi on
chip ec/google/chromeec chip ec/google/chromeec