soc/intel: Add max memory speed into dimm info

Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0.

TEST=check dmidecode dump the max speed.
Handle 0x000C, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 16 GB
        Form Factor: SODIMM
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR5
        Type Detail: Unknown Synchronous
        Speed: 5600 MT/s
        Manufacturer: Micron
        Serial Number: 3f064d84
        Asset Tag: Channel-0-DIMM-0-AssetTag
        Part Number: MTC8C1084S1SC56BG1
        Rank: 1
        Configured Memory Speed: 5200 MT/s
        Minimum Voltage: 1.1 V
        Maximum Voltage: 1.1 V
        Configured Voltage: 1.1 V

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/romstage/romstage.c

@@ -140,7 +140,8 @@ static void save_dimm_info(void)
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
 					src_dimm->SpdModuleType,
-					node);
+					node,
+					meminfo_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/apollolake/meminit_util_apl.c

@@ -83,6 +83,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num)
 				0,
 				src_dimm->MfgId,
 				0,
+				0,
 				0);
 			index++;
 		}

src/soc/intel/apollolake/meminit_util_glk.c

@@ -89,7 +89,8 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num)
 				    0,
 				    src_dimm->MfgId,
 				    src_dimm->SpdModuleType,
-				    node);
+				    node,
+				    memory_info_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/cannonlake/romstage/romstage.c

@@ -108,7 +108,8 @@ static void save_dimm_info(void)
 				memory_info_hob->EccSupport,
 				src_dimm->MfgId,
 				src_dimm->SpdModuleType,
-				0);
+				0,
+				memory_info_hob->MaximumMemoryClockSpeed);
 			index++;
 		}
 	}

src/soc/intel/common/smbios.c

@@ -14,13 +14,17 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
 		u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
 		const char *module_part_num, size_t module_part_number_size,
 		const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
-		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id)
+		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id,
+		u32 max_frequency)
 {
 	dimm->mod_id = mod_id;
 	dimm->mod_type = mod_type;
 	dimm->dimm_size = dimm_capacity;
 	dimm->ddr_type = ddr_type;
+	/* keep ddr_frequency for backward compatible */
 	dimm->ddr_frequency = frequency;
+	dimm->configured_speed_mts = frequency;
+	dimm->max_speed_mts = max_frequency;
 	dimm->rank_per_dimm = rank_per_dimm;
 	dimm->channel_num = channel_id;
 	dimm->dimm_num = dimm_id;

src/soc/intel/common/smbios.h

@@ -14,6 +14,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
 		u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
 		const char *module_part_num, size_t module_part_number_size,
 		const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
-		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id);
+		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id,
+		u32 max_frequency);
 
 #endif /* _COMMON_SMBIOS_H_ */

src/soc/intel/elkhartlake/romstage/romstage.c

@@ -113,7 +113,8 @@ static void save_dimm_info(void)
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
 					src_dimm->SpdModuleType,
-					node);
+					node,
+					meminfo_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/jasperlake/romstage/romstage.c

@@ -113,7 +113,8 @@ static void save_dimm_info(void)
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
 					src_dimm->SpdModuleType,
-					node);
+					node,
+					meminfo_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/meteorlake/romstage/romstage.c

@@ -108,7 +108,8 @@ static void save_dimm_info(void)
 						meminfo_hob->EccSupport,
 					src_dimm->MfgId,
 					src_dimm->SpdModuleType,
-					node);
+					node,
+					meminfo_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/skylake/romstage/romstage.c

@@ -112,7 +112,8 @@ static void save_dimm_info(void)
 				memory_info_hob->EccSupport,
 				src_dimm->MfgId,
 				src_dimm->SpdModuleType,
-				0);
+				0,
+				memory_info_hob->MaximumMemoryClockSpeed);
 			index++;
 		}
 	}

src/soc/intel/tigerlake/romstage/romstage.c

@@ -113,7 +113,8 @@ static void save_dimm_info(void)
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
 					src_dimm->SpdModuleType,
-					node);
+					node,
+					meminfo_hob->MaximumMemoryClockSpeed);
 				index++;
 			}
 		}

src/soc/intel/xeon_sp/cpx/romstage.c

@@ -81,9 +81,6 @@ void save_dimm_info(void)
 					return;
 				}
 				dest_dimm = &mem_info->dimm[index];
-				dest_dimm->max_speed_mts =
-					get_max_memory_speed(src_dimm.commonTck);
-				dest_dimm->configured_speed_mts = hob->memFreq;
 				dimm_info_fill(dest_dimm,
 					src_dimm.DimmSize << 6,
 					0x1a, /* hard-coded memory device type as DDR4 */
@@ -99,7 +96,8 @@ void save_dimm_info(void)
 					true, /* hard-coded as ECC supported */
 					src_dimm.VendorID,
 					src_dimm.actKeyByte2,
-					0);
+					0,
+					get_max_memory_speed(src_dimm.commonTck));
 				index++;
 				num_dimms++;
 			} else if (mainboard_dimm_slot_exists(0, ch, dimm)) {

src/soc/intel/xeon_sp/spr/romstage.c

@@ -304,9 +304,7 @@ void save_dimm_info(void)
 					   the board. */
 					continue;
 				}
-				dest_dimm->max_speed_mts =
+
-					get_max_memory_speed(src_dimm.commonTck);
-				dest_dimm->configured_speed_mts = hob->memFreq;
 				dest_dimm->soc_num = soc;
 
 				if (hob->DramType == SPD_TYPE_DDR5) {
@@ -328,7 +326,8 @@ void save_dimm_info(void)
 					sizeof(src_dimm.PartNumber),
 					(const uint8_t *)&src_dimm.serialNumber[0], data_width,
 					vdd_voltage, true, /* hard-coded as ECC supported */
-					src_dimm.VendorID, src_dimm.actKeyByte2, 0);
+					src_dimm.VendorID, src_dimm.actKeyByte2, 0,
+					get_max_memory_speed(src_dimm.commonTck));
 				dimm_num++;
 			}
 		}