diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig
index f152392602..af11828d2c 100644
--- a/src/mainboard/system76/addw1/Kconfig
+++ b/src/mainboard/system76/addw1/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
diff --git a/src/mainboard/system76/addw1/Makefile.inc b/src/mainboard/system76/addw1/Makefile.inc
index fedde68c13..9d2cef02f4 100644
--- a/src/mainboard/system76/addw1/Makefile.inc
+++ b/src/mainboard/system76/addw1/Makefile.inc
@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
diff --git a/src/mainboard/system76/addw1/acpi/mainboard.asl b/src/mainboard/system76/addw1/acpi/mainboard.asl
index 4e67439c56..2f01acc0bc 100644
--- a/src/mainboard/system76/addw1/acpi/mainboard.asl
+++ b/src/mainboard/system76/addw1/acpi/mainboard.asl
@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {
diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 4f16bbd46e..b7bac0dfb3 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -58,6 +58,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device
diff --git a/src/mainboard/system76/addw1/romstage.c b/src/mainboard/system76/addw1/romstage.c
index 34a426d6f2..4a878db7e4 100644
--- a/src/mainboard/system76/addw1/romstage.c
+++ b/src/mainboard/system76/addw1/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Disable higher memory speeds
 	memupd->FspmConfig.SaOcSupport = 0;
 
diff --git a/src/mainboard/system76/addw1/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h
similarity index 53%
rename from src/mainboard/system76/addw1/include/variant/gpio.h
rename to src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h
index 95d576294f..c78f11b4cd 100644
--- a/src/mainboard/system76/addw1/include/variant/gpio.h
+++ b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/gaze15/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h
similarity index 53%
rename from src/mainboard/system76/gaze15/include/variant/gpio.h
rename to src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h
index 95d576294f..321cd43527 100644
--- a/src/mainboard/system76/gaze15/include/variant/gpio.h
+++ b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig
index 3627cb110b..8568562ead 100644
--- a/src/mainboard/system76/gaze15/Kconfig
+++ b/src/mainboard/system76/gaze15/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc
index 32a409992f..db0fe4f738 100644
--- a/src/mainboard/system76/gaze15/Makefile.inc
+++ b/src/mainboard/system76/gaze15/Makefile.inc
@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl
index b235437c25..610cdd12ba 100644
--- a/src/mainboard/system76/gaze15/acpi/mainboard.asl
+++ b/src/mainboard/system76/gaze15/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index c02a6ec086..64f1e67929 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -57,6 +57,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
diff --git a/src/mainboard/system76/gaze15/romstage.c b/src/mainboard/system76/gaze15/romstage.c
index 02634ba2ad..fdb208b88d 100644
--- a/src/mainboard/system76/gaze15/romstage.c
+++ b/src/mainboard/system76/gaze15/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }
diff --git a/src/mainboard/system76/oryp6/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h
similarity index 53%
rename from src/mainboard/system76/oryp6/include/variant/gpio.h
rename to src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h
index 95d576294f..d1647fc437 100644
--- a/src/mainboard/system76/oryp6/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h
@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85501558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h
new file mode 100644
index 0000000000..0bfd82ed79
--- /dev/null
+++ b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85201558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
diff --git a/src/mainboard/system76/gaze16/Kconfig b/src/mainboard/system76/gaze16/Kconfig
index c8af2d4ca9..3989538ee9 100644
--- a/src/mainboard/system76/gaze16/Kconfig
+++ b/src/mainboard/system76/gaze16/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
diff --git a/src/mainboard/system76/gaze16/acpi/mainboard.asl b/src/mainboard/system76/gaze16/acpi/mainboard.asl
index c982a9ee4c..1cf2a28bca 100644
--- a/src/mainboard/system76/gaze16/acpi/mainboard.asl
+++ b/src/mainboard/system76/gaze16/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }
diff --git a/src/mainboard/system76/gaze16/romstage.c b/src/mainboard/system76/gaze16/romstage.c
index 119c3f5d38..cbe644ea99 100644
--- a/src/mainboard/system76/gaze16/romstage.c
+++ b/src/mainboard/system76/gaze16/romstage.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include "variant.h"
 
 static const struct mb_cfg board_cfg = {
@@ -22,9 +24,21 @@ static const struct mem_spd spd_info = {
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
 	variant_memory_init_params(mupd);
 
-	const bool half_populated = false;
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
 
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }
diff --git a/src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h
index a5e9b17f95..df428ff084 100644
--- a/src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h
@@ -5,6 +5,13 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50151558
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +292,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */
diff --git a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
index 32f0805ac0..08917db764 100644
--- a/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
+++ b/src/mainboard/system76/gaze16/variants/3050/overridetree.cb
@@ -6,15 +6,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
 			register "PcieClkSrcUsage[0]" = "0x42"
 			register "PcieClkSrcClkReq[0]" = "0"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "0" # GFX_CLKREQ0#
-				device generic 0 on end
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
 			end
 		end
 		device ref peg0 on
diff --git a/src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h
index f1d2cdabf5..ebae660ab3 100644
--- a/src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h
@@ -5,6 +5,13 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50e11558
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +292,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */
diff --git a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb
index 881b2c5caf..1c6a05c6f3 100644
--- a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb
+++ b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb
@@ -6,15 +6,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
 			end
 		end
 		device ref peg0 on
diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig
index 9a0a323be9..5d85cbf12d 100644
--- a/src/mainboard/system76/oryp5/Kconfig
+++ b/src/mainboard/system76/oryp5/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
diff --git a/src/mainboard/system76/oryp5/acpi/mainboard.asl b/src/mainboard/system76/oryp5/acpi/mainboard.asl
index 17d2221ab4..f816e3f2da 100644
--- a/src/mainboard/system76/oryp5/acpi/mainboard.asl
+++ b/src/mainboard/system76/oryp5/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
+
 #define EC_GPE_SCI 0x17 /* GPP_B23 */
 #define EC_GPE_SWI 0x26 /* GPP_G6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -9,6 +11,10 @@ Scope (\_SB)
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index bb756166a1..954ec7a70a 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -65,6 +65,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
diff --git a/src/mainboard/system76/oryp5/include/mainboard/gpio.h b/src/mainboard/system76/oryp5/include/mainboard/gpio.h
index c6393beebb..2bfbd100af 100644
--- a/src/mainboard/system76/oryp5/include/mainboard/gpio.h
+++ b/src/mainboard/system76/oryp5/include/mainboard/gpio.h
@@ -3,7 +3,16 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x95e61558
+
+#ifndef __ACPI__
 void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/oryp5/romstage.c b/src/mainboard/system76/oryp5/romstage.c
index 455a2bb919..ec24f532b2 100644
--- a/src/mainboard/system76/oryp5/romstage.c
+++ b/src/mainboard/system76/oryp5/romstage.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
+#include <mainboard/gpio.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow memory speeds higher than 2666 MT/s
 	memupd->FspmConfig.SaOcSupport = 1;
 
diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig
index 0aef4a6047..7e89733c85 100644
--- a/src/mainboard/system76/oryp6/Kconfig
+++ b/src/mainboard/system76/oryp6/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
diff --git a/src/mainboard/system76/oryp6/Makefile.inc b/src/mainboard/system76/oryp6/Makefile.inc
index 2267eb6f9f..3227cf91d5 100644
--- a/src/mainboard/system76/oryp6/Makefile.inc
+++ b/src/mainboard/system76/oryp6/Makefile.inc
@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
diff --git a/src/mainboard/system76/oryp6/acpi/mainboard.asl b/src/mainboard/system76/oryp6/acpi/mainboard.asl
index b235437c25..610cdd12ba 100644
--- a/src/mainboard/system76/oryp6/acpi/mainboard.asl
+++ b/src/mainboard/system76/oryp6/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index 83c96fcfbb..041abaf192 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -62,6 +62,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
diff --git a/src/mainboard/system76/oryp6/romstage.c b/src/mainboard/system76/oryp6/romstage.c
index 8ea791a2d1..44da3d8c46 100644
--- a/src/mainboard/system76/oryp6/romstage.c
+++ b/src/mainboard/system76/oryp6/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct cnl_mb_cfg memcfg = {
@@ -21,6 +23,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	variant_configure_fspm(memupd);
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
diff --git a/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h
new file mode 100644
index 0000000000..697e1ecf51
--- /dev/null
+++ b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x50d31558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
diff --git a/src/mainboard/system76/oryp6/include/variant/romstage.h b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/romstage.h
similarity index 100%
rename from src/mainboard/system76/oryp6/include/variant/romstage.h
rename to src/mainboard/system76/oryp6/variants/oryp6/include/variant/romstage.h
diff --git a/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h
new file mode 100644
index 0000000000..6e1d7dfa12
--- /dev/null
+++ b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x65e51558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
diff --git a/src/mainboard/system76/oryp6/variants/oryp7/include/variant/romstage.h b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/romstage.h
new file mode 100644
index 0000000000..072a485334
--- /dev/null
+++ b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/romstage.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_ROMSTAGE_H
+#define VARIANT_ROMSTAGE_H
+
+#include <fsp/soc_binding.h>
+
+void variant_configure_fspm(FSPM_UPD *memupd);
+
+#endif
diff --git a/src/mainboard/system76/oryp8/Kconfig b/src/mainboard/system76/oryp8/Kconfig
index 9de885fcd9..f57a2621ef 100644
--- a/src/mainboard/system76/oryp8/Kconfig
+++ b/src/mainboard/system76/oryp8/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP8
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
diff --git a/src/mainboard/system76/oryp8/acpi/mainboard.asl b/src/mainboard/system76/oryp8/acpi/mainboard.asl
index c982a9ee4c..0884cdcede 100644
--- a/src/mainboard/system76/oryp8/acpi/mainboard.asl
+++ b/src/mainboard/system76/oryp8/acpi/mainboard.asl
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }
diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb
index ec01d8a40c..cc1c8d0a21 100644
--- a/src/mainboard/system76/oryp8/devicetree.cb
+++ b/src/mainboard/system76/oryp8/devicetree.cb
@@ -92,15 +92,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
 			end
 		end
 		device ref igpu on
diff --git a/src/mainboard/system76/oryp8/include/mainboard/gpio.h b/src/mainboard/system76/oryp8/include/mainboard/gpio.h
index c6393beebb..dc5066e9f1 100644
--- a/src/mainboard/system76/oryp8/include/mainboard/gpio.h
+++ b/src/mainboard/system76/oryp8/include/mainboard/gpio.h
@@ -3,7 +3,16 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x65f11558
+
+#ifndef __ACPI__
 void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
+#endif
 
 #endif
diff --git a/src/mainboard/system76/oryp8/romstage.c b/src/mainboard/system76/oryp8/romstage.c
index 64cc844064..6e178f5b69 100644
--- a/src/mainboard/system76/oryp8/romstage.c
+++ b/src/mainboard/system76/oryp8/romstage.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
+#include <mainboard/gpio.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
@@ -23,6 +25,18 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Enable M.2 PCIE 4.0 and PEG1
 	mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
 
diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig
index ea2419b16d..3ca5218211 100644
--- a/src/mainboard/system76/tgl-u/Kconfig
+++ b/src/mainboard/system76/tgl-u/Kconfig
@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
@@ -69,4 +70,15 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+# For galp5 with dGPU
+if DRIVERS_GFX_NVIDIA
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x1c
+
+endif # DRIVERS_GFX_NVIDIA
+
 endif
diff --git a/src/mainboard/system76/tgl-u/acpi/mainboard.asl b/src/mainboard/system76/tgl-u/acpi/mainboard.asl
index c982a9ee4c..6adceba1fd 100644
--- a/src/mainboard/system76/tgl-u/acpi/mainboard.asl
+++ b/src/mainboard/system76/tgl-u/acpi/mainboard.asl
@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(BOARD_SYSTEM76_GALP5)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+#if CONFIG(BOARD_SYSTEM76_GALP5)
+		Scope (RP01) { // Remapped from RP05
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
index 1b4249c3f7..ce3ecc3a66 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -143,15 +143,11 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[4]" = "1"
 			register "PcieClkSrcUsage[2]" = "4"
 			register "PcieClkSrcClkReq[2]" = "2"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
-				register "enable_delay_ms" = "16"
-				register "enable_off_delay_ms" = "4"
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "2" # PEG_CLKREQ#
-				device generic 0 on end
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
 			end
 		end
 		device ref pcie_rp9 on
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c
index eb4fd3974b..f40b8f51a0 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c
+++ b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
@@ -18,5 +20,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Allow memory clocks higher than 2933 MHz
+	mupd->FspmConfig.SaOcSupport = 1;
+
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }