20090819-2-trim-down-cbfs:
CBFS uses sprintf, which requires vtxprintf, which requires (in the current design) a nested function. That works on x86, but on PPC this requires a trampoline. In the ROM stage, this is not available, so remove the single use of sprintf and replace it with a direct string handler - it's only used to fill in fixed-length hex values. 20090819-3-more-noreturns-in-romcc: Mark two more functions in romcc as noreturn. Helps clang's scan-build a bit 20090819-4-cbfsify-ppc: Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and not complete yet. 20090819-5-fix-ppc-build: The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat plausible value. With fixes to tohex* functions as discussed on the list, and correct function names. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -13,7 +13,6 @@ if CONFIG_CBFS
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if CONFIG_USE_FAILOVER_IMAGE
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else
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initobject /src/lib/cbfs.o
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initobject /src/console/vsprintf.o
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initobject /src/lib/lzma.o
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end
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end
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@ -1,3 +1,4 @@
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uses CONFIG_CBFS
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ldscript init/ldscript.lb
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makerule coreboot.strip
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@ -10,6 +11,11 @@ makerule coreboot.rom
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action "cp $< $@"
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end
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if CONFIG_CBFS
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initobject /src/lib/cbfs.o
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initobject /src/lib/lzma.o
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end
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dir init
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dir lib
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dir boot
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@ -5,12 +5,7 @@
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#include <board.h>
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#include <sdram.h>
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extern unsigned _iseg[];
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extern unsigned _liseg[];
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extern unsigned _eliseg[];
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void (*payload)(void) = (void (*)(void))_iseg;
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#include <cbfs.h>
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/*
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* At this point we're running out of flash with our
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@ -25,8 +20,7 @@ extern void flush_dcache(void);
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void ppc_main(void)
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{
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unsigned *from;
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unsigned *to;
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void (*payload)(void);
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/*
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* very early board initialization
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@ -49,15 +43,9 @@ void ppc_main(void)
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flush_dcache();
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/*
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* Relocate payload (text & data) if necessary
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* Relocate payload (text & data)
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*/
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if (_liseg != _iseg) {
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from = _liseg;
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to = _iseg;
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while (from < _eliseg)
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*to++ = *from++;
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}
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payload = cbfs_load_stage("fallback/coreboot_ram");
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payload();
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/* NOT REACHED */
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@ -124,13 +124,27 @@ struct cbfs_stage *cbfs_find_file(const char *name, int type)
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return (void *) CBFS_SUBHEADER(file);
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}
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static int tohex4(unsigned int c)
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{
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return (c<=9)?(c+'0'):(c-10+'a');
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}
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static void tohex16(unsigned int val, char* dest)
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{
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dest[0]=tohex4(val>>12);
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dest[1]=tohex4((val>>8) & 0xf);
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dest[2]=tohex4((val>>4) & 0xf);
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dest[3]=tohex4(val & 0xf);
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}
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void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest)
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{
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char name[17];
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char name[17]="pciXXXX,XXXX.rom";
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struct cbfs_optionrom *orom;
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u8 *src;
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sprintf(name,"pci%04x,%04x.rom", vendor, device);
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tohex16(vendor, name+3);
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tohex16(device, name+8);
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orom = (struct cbfs_optionrom *)
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cbfs_find_file(name, CBFS_TYPE_OPTIONROM);
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@ -106,6 +106,7 @@ default CONFIG_FS_FAT=1
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default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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default CONFIG_ROM_SIZE=1048576
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default CONFIG_ROM_IMAGE_SIZE=160*1024
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## Board has fixed size RAM
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default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
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@ -94,8 +94,8 @@ default CONFIG_FS_FAT=1
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default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
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# coreboot must fit into 128KB
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default CONFIG_ROM_IMAGE_SIZE=131072
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default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
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default CONFIG_ROM_IMAGE_SIZE=160*1024
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default CONFIG_ROM_SIZE=384*1024
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default CONFIG_PAYLOAD_SIZE=262144
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# Set stack and heap sizes (stage 2)
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@ -96,6 +96,7 @@ default CONFIG_IDE_OFFSET=0
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# ROM is 1Mb
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default CONFIG_ROM_SIZE=1048576
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default CONFIG_ROM_IMAGE_SIZE=128*1024
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# Set stack and heap sizes (stage 2)
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default CONFIG_STACK_SIZE=0x10000
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