sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cannonlake: Update UPD from device switch

Browse Source 
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.

BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.

Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
2018-07-31 17:23:32 -07:00
committed by Patrick Georgi
parent 80346d0490
commit b269f873b0
9 changed files with 47 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

2
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
View File

@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
View File

@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

4
src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
View File

@@ -6,10 +6,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "HeciEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
@@ -30,7 +27,6 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "SataEnable" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"