cpu/x86/smm: Promote smm_subregion()

No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.

Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/drivers/intel/fsp1_1/car.c

@@ -19,9 +19,9 @@
 #include <commonlib/helpers.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
-#include <fsp/memmap.h>
 #include <program_loading.h>
 
 /* platform_enter_postcar() determines the stack to use after

src/drivers/intel/fsp1_1/include/fsp/memmap.h

@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_MEMMAP_H_
-#define _COMMON_MEMMAP_H_
-
-#include <types.h>
-
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
-#endif /* _COMMON_MEMMAP_H_ */

src/drivers/intel/fsp1_1/raminit.c

@@ -19,7 +19,7 @@
 #include <cf9_reset.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <lib.h> /* hexdump */

src/drivers/intel/fsp1_1/ramstage.c

@@ -17,7 +17,7 @@
 #include <bootmode.h>
 #include <arch/acpi.h>
 #include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <fsp/ramstage.h>
 #include <fsp/util.h>
 #include <lib.h>

src/drivers/intel/fsp1_1/stage_cache.c

@@ -15,7 +15,7 @@
  */
 
 #include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <stage_cache.h>
 
 void stage_cache_external_region(void **base, size_t *size)

src/drivers/intel/fsp2_0/include/fsp/memmap.h

@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_MEMMAP_H_
-#define _COMMON_MEMMAP_H_
-
-#include <types.h>
-
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
-#endif /* _COMMON_MEMMAP_H_ */

src/include/cpu/x86/smm.h

@@ -583,4 +583,26 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params);
 void *backup_default_smm_area(void);
 void restore_default_smm_area(void *smm_save_area);
 
+/*
+ * Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG.
+ */
+void smm_region(void **start, size_t *size);
+void smm_region_info(void **start, size_t *size);
+
+enum {
+	/* SMM handler area. */
+	SMM_SUBREGION_HANDLER,
+	/* SMM cache region. */
+	SMM_SUBREGION_CACHE,
+	/* Chipset specific area. */
+	SMM_SUBREGION_CHIPSET,
+	/* Total sub regions supported. */
+	SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on success, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
 #endif /* CPU_X86_SMM_H */

src/soc/amd/picasso/cpu.c

@@ -18,6 +18,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/lapic.h>
 #include <device/device.h>

src/soc/amd/picasso/include/soc/northbridge.h

@@ -99,29 +99,8 @@
 #define NB_CAPABILITIES2	0x84
 #define   CMP_CAP_MASK		0xff
 
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
 void amd_initcpuio(void);
 
-/*
- * Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG.
- */
-void smm_region_info(void **start, size_t *size);
-/*
- * Fills in the start and size for the requested SMM subregion. Returns
- * 0 on success, < 0 on failure.
- */
-int smm_subregion(int sub, void **start, size_t *size);
 void domain_enable_resources(struct device *dev);
 void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);

src/soc/amd/picasso/ramtop.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>

src/soc/amd/picasso/romstage.c

@@ -19,6 +19,7 @@
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>

src/soc/amd/stoneyridge/cpu.c

@@ -18,6 +18,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/lapic.h>
 #include <device/device.h>

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -99,27 +99,6 @@
 #define NB_CAPABILITIES2	0x84
 #define   CMP_CAP_MASK		0xff
 
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
-/*
- * Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG.
- */
-void smm_region_info(void **start, size_t *size);
-/*
- * Fills in the start and size for the requested SMM subregion. Returns
- * 0 on success, < 0 on failure.
- */
-int smm_subregion(int sub, void **start, size_t *size);
 void domain_enable_resources(struct device *dev);
 void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);

src/soc/amd/stoneyridge/ramtop.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>

src/soc/amd/stoneyridge/romstage.c

@@ -19,6 +19,7 @@
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>

src/soc/intel/apollolake/cpu.c

@@ -29,10 +29,10 @@
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
-#include <fsp/memmap.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/mp_init.h>

src/soc/intel/apollolake/memmap.c

@@ -18,8 +18,8 @@
 #include <assert.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <device/pci.h>
-#include <fsp/memmap.h>
 #include <intelblocks/smm.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>

src/soc/intel/apollolake/romstage.c

@@ -27,10 +27,10 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/pae.h>
 #include <delay.h>
+#include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <fsp/api.h>
-#include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/lpc_lib.h>

src/soc/intel/braswell/cpu.c

@@ -26,7 +26,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <fsp/memmap.h>
 #include <reg_script.h>
 #include <soc/iosf.h>
 #include <soc/msr.h>

src/soc/intel/braswell/memmap.c

@@ -15,7 +15,7 @@
  */
 
 #include <cbmem.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <soc/iosf.h>
 #include <soc/smm.h>
 

src/soc/intel/braswell/northcluster.c

@@ -21,8 +21,8 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp/memmap.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/x86/smm.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>

src/soc/intel/cannonlake/include/soc/smm.h

@@ -19,7 +19,7 @@
 
 #include <stdint.h>
 #include <cpu/x86/msr.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <soc/gpio.h>
 
 struct ied_header {

src/soc/intel/common/block/include/intelblocks/smm.h

@@ -32,7 +32,5 @@
  */
 void smm_southbridge_clear_state(void);
 void smm_southbridge_enable(uint16_t pm1_events);
-/* API to get SMM region start and size based on Host Bridge register */
-void smm_region_info(void **start, size_t *size);
 
 #endif

src/soc/intel/common/block/smm/smm.c

@@ -18,7 +18,6 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <fsp/memmap.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smm.h>
 #include <intelblocks/systemagent.h>

src/soc/intel/denverton_ns/cpu.c

@@ -21,6 +21,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
 #include <device/pci.h>

src/soc/intel/denverton_ns/include/soc/smm.h

@@ -24,25 +24,6 @@ struct smm_relocation_attrs {
 	uint32_t smrr_mask;
 };
 
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
 #if !defined(__PRE_RAM__) && !defined(__SMM___)
 #include <stdint.h>
 void southcluster_smm_clear_state(void);

src/soc/intel/denverton_ns/memmap.c

@@ -16,12 +16,12 @@
 
 #include <cbmem.h>
 #include <assert.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
-#include <soc/smm.h>
 #include <lib.h>
 
 /* Returns base of requested region encoded in the system agent. */

src/soc/intel/denverton_ns/romstage.c

@@ -20,6 +20,7 @@
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
 #include <soc/fiamux.h>
 #include <device/mmio.h>
@@ -29,7 +30,6 @@
 #include <soc/pmc.h>
 #include <soc/romstage.h>
 #include <soc/smbus.h>
-#include <soc/smm.h>
 #include <soc/soc_util.h>
 #include <soc/hob_mem.h>
 

src/soc/intel/icelake/include/soc/smm.h

@@ -18,7 +18,7 @@
 
 #include <stdint.h>
 #include <cpu/x86/msr.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <soc/gpio.h>
 
 struct ied_header {

src/soc/intel/skylake/include/soc/smm.h

@@ -19,7 +19,7 @@
 
 #include <stdint.h>
 #include <cpu/x86/msr.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <intelblocks/smihandler.h>
 #include <soc/gpio.h>
 

src/soc/intel/skylake/memmap.c

@@ -18,9 +18,9 @@
 #include <device/mmio.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/memmap.h>
 #include <intelblocks/ebda.h>
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -18,11 +18,11 @@
 #include <assert.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
-#include <fsp/memmap.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
 #include <smbios.h>