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cpu/x86/lapic: Drop xapic_write_atomic()

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Remove code, which was only needed for B and C2 stepping
of P54C. The linux kernel source has commentary on X86_BUG_11AP:

 * See if we have a good local APIC by checking for buggy Pentia,
 * i.e. all B steppings and the C2 stepping of P54C when using their
 * integrated APIC (see 11AP erratum in "Pentium Processor
 * Specification Update")

Change-Id: Iec10335f603674bcef2e7494831cf11200795d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
2021-05-31 14:41:15 +03:00
parent 253c356c2b
commit b31b033ccc
2 changed files with 4 additions and 15 deletions
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2
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -128,7 +128,7 @@ static int lapic_start_cpu(unsigned long apicid)
printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) { if (lapic_read(LAPIC_ESR)) {
printk(BIOS_ERR, "Try to reset ESR\n"); printk(BIOS_ERR, "Try to reset ESR\n");
xapic_write_atomic(LAPIC_ESR, 0); lapic_write(LAPIC_ESR, 0);
printk(BIOS_ERR, "ESR is 0x%x\n", printk(BIOS_ERR, "ESR is 0x%x\n",
lapic_read(LAPIC_ESR)); lapic_read(LAPIC_ESR));
} }

17
src/include/cpu/x86/lapic.h
View File

@@ -18,21 +18,10 @@ static __always_inline void xapic_write(unsigned int reg, uint32_t v)
write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v);
} }
static inline void xapic_write_atomic(unsigned long reg, uint32_t v)
{
volatile uint32_t *ptr;
ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg);
asm volatile ("xchgl %0, %1\n"
: "+r" (v), "+m" (*(ptr))
: : "memory", "cc");
}
static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid)
{ {
xapic_write_atomic(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
xapic_write_atomic(LAPIC_ICR, icrlow); xapic_write(LAPIC_ICR, icrlow);
} }
static __always_inline int xapic_busy(void) static __always_inline int xapic_busy(void)
@@ -114,7 +103,7 @@ static __always_inline void lapic_update32(unsigned int reg, uint32_t mask, uint
value = xapic_read(reg); value = xapic_read(reg);
value &= mask; value &= mask;
value |= or; value |= or;
xapic_write_atomic(reg, value); xapic_write(reg, value);
} }
} }