* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
  and drop it from the individual romstage.c files.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>

 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/console/console.c

@@ -95,6 +95,10 @@ int console_tst_byte(void)
 
 void console_init(void)
 {
+#if CONFIG_USBDEBUG
+	enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+	early_usbdebug_init();
+#endif
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif

src/mainboard/amd/bimini_fam10/romstage.c

@@ -110,12 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb800_lpc_init();
 
 	uart_init();
-#if CONFIG_USBDEBUG
-	sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/amd/dbm690t/romstage.c

@@ -94,11 +94,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/amd/mahogany/romstage.c

@@ -93,11 +93,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/amd/pistachio/romstage.c

@@ -91,11 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * and it doesn't require any special setup. */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	post_code(0x03);

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -105,13 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/asrock/939a785gmh/romstage.c

@@ -160,11 +160,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/asus/m2n-e/romstage.c

@@ -123,10 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_mb_resource_map();
 	uart_init();
 	report_bist_failure(bist);
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);

src/mainboard/asus/m4a78-em/romstage.c

@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/asus/m4a785-m/romstage.c

@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/getac/p470/romstage.c

@@ -288,10 +288,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -147,10 +147,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
         console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -150,10 +150,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
         console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -102,11 +102,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_disable_reboot();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 	printk(BIOS_DEBUG, "\n");
 

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_disable_reboot();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);

src/mainboard/ibase/mb899/romstage.c

@@ -239,11 +239,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -107,13 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/intel/d945gclf/romstage.c

@@ -200,11 +200,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/jetway/pa78vm5/romstage.c

@@ -112,13 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/kontron/986lcd-m/romstage.c

@@ -337,11 +337,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/kontron/kt690/romstage.c

@@ -96,11 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/lenovo/x60/romstage.c

@@ -242,11 +242,6 @@ void main(unsigned long bist)
 		uart_init();
 	}
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/msi/ms7260/romstage.c

@@ -139,10 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_mb_resource_map();
 	uart_init();
 	report_bist_failure(bist); /* Halt upon BIST failure. */
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -140,10 +140,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

src/mainboard/roda/rk886ex/romstage.c

@@ -272,11 +272,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -125,12 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_disable_wideio(0);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/technexion/tim5690/romstage.c

@@ -100,11 +100,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/technexion/tim8690/romstage.c

@@ -95,11 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/tyan/s2912/romstage.c

@@ -136,10 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);

src/southbridge/amd/sb600/Kconfig

@@ -36,6 +36,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xe0
 
+config USBDEBUG_DEFAULT_PORT
+	int
+	default 0
+
 choice
 	prompt "SATA Mode"
 	default SATA_MODE_IDE

src/southbridge/amd/sb600/enable_usbdebug.c

@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
 	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-void sb600_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 

src/southbridge/amd/sb600/sb600.h

@@ -40,5 +40,5 @@ void sb600_enable(device_t dev);
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
-void sb600_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB600_H */

src/southbridge/amd/sb700/enable_usbdebug.c

@@ -45,7 +45,7 @@ void set_debug_port(unsigned int port)
  * This code currently only supports the first one, i.e., USB Debug devices
  * attached to physical USB ports belonging to the first EHCI device.
  */
-void sb7xx_51xx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 

src/southbridge/amd/sb700/sb700.h

@@ -75,5 +75,5 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb7xx_51xx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB700_H */

src/southbridge/amd/sb800/enable_usbdebug.c

@@ -43,7 +43,7 @@ void set_debug_port(unsigned int port)
 }
 
 
-void sb800_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5),
 			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

src/southbridge/amd/sb800/sb800.h

@@ -58,7 +58,7 @@ void sb800_clk_output_48Mhz(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb800_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #else
 void sb800_enable(device_t dev);
 void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);

src/southbridge/intel/i82801gx/Kconfig

@@ -24,11 +24,19 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT
 
+if SOUTHBRIDGE_INTEL_I82801GX
+
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+	default 0xfef00000
 
 config EHCI_DEBUG_OFFSET
 	hex
-	default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+	default 0xa0
+
+config USBDEBUG_DEFAULT_PORT
+	int
+	default 1 
+
+endif
 

src/southbridge/intel/i82801gx/i82801gx.h

@@ -46,7 +46,7 @@ extern void i82801gx_enable(device_t dev);
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 #endif
-void i82801gx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #define MAINBOARD_POWER_OFF	0

src/southbridge/intel/i82801gx/usb_debug.c

@@ -31,7 +31,7 @@ void set_debug_port(unsigned int port)
 	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-void i82801gx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
 	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */

src/southbridge/intel/sch/usb_debug.c

@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
 	/* Not needed, the southbridges hardcode physical USB port 1. */
 }
 
-void sch_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
 	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */

src/southbridge/nvidia/ck804/ck804.h

@@ -24,7 +24,7 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
-void ck804_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 
 extern struct pci_operations ck804_pci_ops;
 

src/southbridge/nvidia/ck804/enable_usbdebug.c

@@ -46,7 +46,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void ck804_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 

src/southbridge/nvidia/mcp55/enable_usbdebug.c

@@ -40,7 +40,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void mcp55_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 

src/southbridge/nvidia/mcp55/mcp55.h

@@ -35,7 +35,7 @@ extern struct pci_operations mcp55_pci_ops;
 #else
 #if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-void mcp55_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 #endif
 

src/southbridge/sis/sis966/enable_usbdebug.c

@@ -42,7 +42,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void sis966_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 

src/southbridge/sis/sis966/sis966.h

@@ -40,7 +40,7 @@ void sis966_enable(device_t dev);
 #endif
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void sis966_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #endif /* SIS966_H */