cmos: Rename the CMOS related functions.

Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.

This CL also opportunistically cleans up some style problems in this file.

Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)

Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.

Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/southbridge/amd/agesa/hudson/lpc.c

@@ -70,14 +70,14 @@ static void lpc_init(device_t dev)
 	byte |= 1 << 0 | 1 << 3;
 	pci_write_config8(dev, 0xBB, byte);
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 
 	/* Initialize the real time clock.
-	 * The 0 argument tells rtc_init not to
+	 * The 0 argument tells cmos_init not to
 	 * update CMOS unless it is invalid.
-	 * 1 tells rtc_init to always initialize the CMOS.
+	 * 1 tells cmos_init to always initialize the CMOS.
 	 */
-	rtc_init(0);
+	cmos_init(0);
 }
 
 static void hudson_lpc_read_resources(device_t dev)

src/southbridge/amd/amd8111/lpc.c

@@ -77,7 +77,7 @@ static void lpc_init(struct device *dev)
 	}
 
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize isa dma */
 	isa_dma_init();

src/southbridge/amd/cimx/sb700/late.c

@@ -80,14 +80,14 @@ static void lpc_init(device_t dev)
 {
 	printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 
 	/* Initialize the real time clock.
-	 * The 0 argument tells rtc_init not to
+	 * The 0 argument tells cmos_init not to
 	 * update CMOS unless it is invalid.
-	 * 1 tells rtc_init to always initialize the CMOS.
+	 * 1 tells cmos_init to always initialize the CMOS.
 	 */
-	rtc_init(0);
+	cmos_init(0);
 
 	setup_i8259(); /* Initialize i8259 pic */
 	setup_i8254(); /* Initialize i8254 timers */

src/southbridge/amd/cimx/sb800/late.c

@@ -132,14 +132,14 @@ static void lpc_init(device_t dev)
 {
 	printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 
 	/* Initialize the real time clock.
-	 * The 0 argument tells rtc_init not to
+	 * The 0 argument tells cmos_init not to
 	 * update CMOS unless it is invalid.
-	 * 1 tells rtc_init to always initialize the CMOS.
+	 * 1 tells cmos_init to always initialize the CMOS.
 	 */
-	rtc_init(0);
+	cmos_init(0);
 
 	setup_i8259(); /* Initialize i8259 pic */
 	setup_i8254(); /* Initialize i8254 timers */

src/southbridge/amd/cimx/sb900/late.c

@@ -102,14 +102,14 @@ static void lpc_init(device_t dev)
 	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
 	/* SB Configure HPET base and enable bit */
 //-	hpetInit(sb_config, &(sb_config->BuildParameters));
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 
 	/* Initialize the real time clock.
-	 * The 0 argument tells rtc_init not to
+	 * The 0 argument tells cmos_init not to
 	 * update CMOS unless it is invalid.
-	 * 1 tells rtc_init to always initialize the CMOS.
+	 * 1 tells cmos_init to always initialize the CMOS.
 	 */
-	rtc_init(0);
+	cmos_init(0);
 
 	setup_i8259(); /* Initialize i8259 pic */
 	setup_i8254(); /* Initialize i8254 timers */

src/southbridge/amd/cs5536/cs5536.c

@@ -245,7 +245,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
 	msr.lo = RTC_MONA;
 	wrmsr(MDD_RTC_MONA_IND, msr);
 
-	rtc_init(0);
+	cmos_init(0);
 
 	isa_dma_init();
 }

src/southbridge/amd/sb600/lpc.c

@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
 	byte &= ~(1 << 1);
 	pci_write_config8(dev, 0x78, byte);
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 }
 
 static void sb600_lpc_read_resources(device_t dev)

src/southbridge/amd/sb600/sm.c

@@ -169,7 +169,7 @@ static void sm_init(device_t dev)
 	/* ab index */
 	pci_write_config32(dev, 0xF0, AB_INDX);
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
 	abcfg_reg(0x10060, 9 << 17, 9 << 17);

src/southbridge/amd/sb700/lpc.c

@@ -90,7 +90,7 @@ static void lpc_init(device_t dev)
 	}
 #endif
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 }
 
 void backup_top_of_ram(uint64_t ramtop)

src/southbridge/amd/sb700/sm.c

@@ -197,7 +197,7 @@ static void sm_init(device_t dev)
 	/* ab index */
 	pci_write_config32(dev, 0xF0, AB_INDX);
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* 4.3 Enabling Upstream DMA Access */
 	axcfg_reg(0x04, 1 << 2, 1 << 2);

src/southbridge/amd/sb800/lpc.c

@@ -67,7 +67,7 @@ static void lpc_init(device_t dev)
 	byte |= 1 << 0 | 1 << 3;
 	pci_write_config8(dev, 0xBB, byte);
 
-	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+	cmos_check_update_date(RTC_HAS_ALTCENTURY);
 }
 
 static void sb800_lpc_read_resources(device_t dev)

src/southbridge/amd/sb800/sm.c

@@ -111,7 +111,7 @@ static void sm_init(device_t dev)
 	pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
 	pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	byte = pm_ioread(0x8);
 	byte |= 1 << 2 | 1 << 4;

src/southbridge/broadcom/bcm5785/lpc.c

@@ -33,7 +33,7 @@
 static void lpc_init(device_t dev)
 {
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize isa dma */
 	isa_dma_init();

src/southbridge/dmp/vortex86ex/southbridge.c

@@ -595,7 +595,7 @@ static void southbridge_init(struct device *dev)
 	pci_routing_fixup(dev);
 
 	fix_cmos_rtc_time();
-	rtc_init(0);
+	cmos_init(0);
 	/* Check keyboard controller ready. If timeout, reload firmware code
 	 * and try again.
 	 */

src/southbridge/intel/bd82x6x/lpc.c

@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 /* CougarPoint PCH Power Management init */

src/southbridge/intel/esb6300/lpc.c

@@ -297,7 +297,7 @@ static void lpc_init(struct device *dev)
 	esb6300_gpio_init(dev);
 
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize isa dma */
 	isa_dma_init();

src/southbridge/intel/fsp_bd82x6x/lpc.c

@@ -305,7 +305,7 @@ static void pch_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 /* CougarPoint PCH Power Management init */

src/southbridge/intel/fsp_rangeley/early_init.c

@@ -69,7 +69,7 @@ static void reset_rtc(void)
 		write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
 	}
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 void rangeley_sb_early_initialization(void)

src/southbridge/intel/i3100/lpc.c

@@ -375,7 +375,7 @@ static void lpc_init(struct device *dev)
 	i3100_gpio_init(dev);
 
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize isa dma */
 	isa_dma_init();

src/southbridge/intel/i82371eb/isa.c

@@ -64,7 +64,7 @@ static void isa_init(struct device *dev)
 	u32 reg32;
 
 	/* Initialize the real time clock (RTC). */
-	rtc_init(0);
+	cmos_init(0);
 
 	/*
 	 * Enable special cycles, needed for soft poweroff.

src/southbridge/intel/i82801ax/lpc.c

@@ -190,7 +190,7 @@ static void i82801ax_rtc_init(struct device *dev)
 	}
 	reg32 = pci_read_config32(dev, GEN_STA);
 	rtc_failed |= reg32 & (1 << 2);
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 
 	/* Enable access to the upper 128 byte bank of CMOS RAM. */
 	pci_write_config8(dev, RTC_CONF, 0x04);

src/southbridge/intel/i82801bx/lpc.c

@@ -205,7 +205,7 @@ static void i82801bx_rtc_init(struct device *dev)
 	}
 	reg32 = pci_read_config32(dev, GEN_STS);
 	rtc_failed |= reg32 & (1 << 2);
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 
 	/* Enable access to the upper 128 byte bank of CMOS RAM. */
 	pci_write_config8(dev, RTC_CONF, 0x04);

src/southbridge/intel/i82801cx/lpc.c

@@ -108,7 +108,7 @@ static void i82801cx_rtc_init(struct device *dev)
     dword = pci_read_config32(dev, GEN_STS);
     rtc_failed |= dword & (1 << 2);
 
-    rtc_init(rtc_failed);
+    cmos_init(rtc_failed);
 }
 
 

src/southbridge/intel/i82801dx/lpc.c

@@ -200,7 +200,7 @@ static void i82801dx_rtc_init(struct device *dev)
 	}
 	reg32 = pci_read_config32(dev, GEN_STS);
 	rtc_failed |= reg32 & (1 << 2);
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 
 	/* Enable access to the upper 128 byte bank of CMOS RAM. */
 	pci_write_config8(dev, RTC_CONF, 0x04);

src/southbridge/intel/i82801ex/lpc.c

@@ -308,7 +308,7 @@ static void lpc_init(struct device *dev)
 	i82801ex_gpio_init(dev);
 
 	/* Initialize the real time clock */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize isa dma */
 	isa_dma_init();

src/southbridge/intel/i82801gx/lpc.c

@@ -294,7 +294,7 @@ static void i82801gx_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 static void enable_hpet(void)

src/southbridge/intel/i82801ix/lpc.c

@@ -326,7 +326,7 @@ static void i82801ix_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 static void enable_hpet(void)

src/southbridge/intel/ibexpeak/lpc.c

@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 static void mobile5_pm_init(struct device *dev)

src/southbridge/intel/lynxpoint/lpc.c

@@ -301,7 +301,7 @@ static void pch_rtc_init(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
-	rtc_init(rtc_failed);
+	cmos_init(rtc_failed);
 }
 
 /* LynxPoint PCH Power Management init */

src/southbridge/nvidia/ck804/lpc.c

@@ -162,7 +162,7 @@ static void lpc_init(device_t dev)
 		outb(byte, 0x70);
 
 	/* Initialize the real time clock (RTC). */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize ISA DMA. */
 	isa_dma_init();

src/southbridge/nvidia/mcp55/lpc.c

@@ -152,7 +152,7 @@ static void lpc_init(device_t dev)
 		outb(byte, 0x70);
 
 	/* Initialize the real time clock. */
-	rtc_init(0);
+	cmos_init(0);
 
 	/* Initialize ISA DMA. */
 	isa_dma_init();

src/southbridge/sis/sis966/lpc.c

@@ -148,7 +148,7 @@ static void lpc_init(device_t dev)
         }
 
         /* Initialize the real time clock */
-        rtc_init(0);
+        cmos_init(0);
 
         /* Initialize isa dma */
         isa_dma_init();

src/southbridge/via/vt8231/lpc.c

@@ -121,7 +121,7 @@ static void vt8231_init(struct device *dev)
 	//ethernet_fixup();
 
 	// Start the rtc
-	rtc_init(0);
+	cmos_init(0);
 }
 
 static void vt8231_read_resources(device_t dev)

src/southbridge/via/vt8235/lpc.c

@@ -209,7 +209,7 @@ static void vt8235_init(struct device *dev)
 	pci_write_config8(dev, 0x40, 0x54);
 
 	// Start the rtc
-	rtc_init(0);
+	cmos_init(0);
 }
 
 /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this

src/southbridge/via/vt8237r/lpc.c

@@ -565,7 +565,7 @@ static void vt8237_common_init(struct device *dev)
 	setup_pm(dev);
 
 	/* Start the RTC. */
-	rtc_init(0);
+	cmos_init(0);
 }
 
 static void vt8237r_read_resources(device_t dev)