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soc/intel/skylake: Wrap lines at 80 columns

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Fix the following warning detected by checkpatch:

WARNING: line over 80 characters

TEST=Build for glados

Change-Id: I79341f46ca06ac052f987975ccaf975470d27806
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18867
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Lee Leahy
2017-03-16 16:44:36 -07:00
parent 573564cca8
commit b439a92939
8 changed files with 39 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/skylake/chip.h
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@@ -265,9 +265,10 @@ struct soc_intel_skylake_config {
u8 LockDownConfigBiosLock;
/*
* Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a
* '1' and InSMM.STS must be '1' also in order to write to BIOS regions of
* SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The
* BIOS must set the EISS bit while BIOS Guard support is enabled.
* '1' and InSMM.STS must be '1' also in order to write to BIOS regions
* of SPI Flash. If this bit is clear, then the InSMM.STS is a don't
* care. The BIOS must set the EISS bit while BIOS Guard support is
* enabled.
*/
u8 LockDownConfigSpiEiss;
/* Subsystem Vendor ID of the PCH devices*/
@@ -325,7 +326,8 @@ struct soc_intel_skylake_config {
*/
u8 PmConfigPciClockRun;
/*
* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled
* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
* 1: Enabled
*/
u8 PmConfigSlpStrchSusUp;
/*
@@ -349,7 +351,9 @@ struct soc_intel_skylake_config {
u8 PmConfigPwrCycDur;
/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
u8 SerialIrqConfigSirqEnable;
/* Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode.*/
/* Serial IRQ Mode Select. Values: 0: PchQuietMode,
* 1: PchContinuousMode.
*/
u8 SerialIrqConfigSirqMode;
/*
* Start Frame Pulse Width.