mb/amd/birman: add function to update MPIO config in devicetree

Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end
numbers need to be adjusted to take that into account. When the Kconfig
options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses
both PICe lanes that are available for those two devices, so the MPIO
descriptor information the devicetree needs to be updated accordingly
and the bridge to the PCIe port that doesn't have any lane left needs to
be disabled. Two other PCIe devices will be disabled when the
corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have
the value that results in the device being disabled via some GPIO driven
by the EC. Since the code is specific to the openSIL case, only include
it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>

src/mainboard/amd/birman/Makefile.mk

@@ -9,6 +9,7 @@ romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c
 
 ramstage-y += chromeos.c
 ramstage-y += gpio.c
+ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c
 ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c
 ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c
 

src/mainboard/amd/birman/mainboard.c

@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <types.h>
 #include "gpio.h"
+#include "update_devicetree.h"
 
 /* TODO: Update for birman */
 
@@ -58,6 +59,9 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
 static void mainboard_init(void *chip_info)
 {
 	mainboard_program_gpios();
+
+	if (CONFIG(BOARD_AMD_BIRMAN_PHOENIX_OPENSIL))
+		mainboard_update_devicetree_opensil();
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/amd/birman/update_devicetree.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_UPDATE_DEVICETREE_H
+#define MAINBOARD_UPDATE_DEVICETREE_H
+
+void mainboard_update_devicetree_opensil(void);
+
+#endif  /* MAINBOARD_UPDATE_DEVICETREE_H */

src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/soc_util.h>
+#include <vendorcode/amd/opensil/stub/mpio/chip.h>
+#include "update_devicetree.h"
+
+static void mainboard_update_mpio(void)
+{
+	struct device *mxm_bridge = DEV_PTR(gpp_bridge_1_1);
+	struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2);
+	struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2);
+	struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3);
+	struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge);
+
+	/* Phoenix 2 has less PCIe lanes than Phoenix */
+	if (get_soc_type() == SOC_PHOENIX2) {
+		mxm_bridge_cfg->end_lane = 3;
+		ssd1_bridge_cfg->end_lane = 9;
+	}
+	if (!CONFIG(ENABLE_EVAL_CARD)) {
+		mxm_bridge->enabled = false;
+	}
+	if (CONFIG(DISABLE_DT_M2)) {
+		ssd1_bridge->enabled = false;
+	}
+	/* When the WLAN card uses 2 lanes, the WWAN card can't be used */
+	if (CONFIG(WLAN01)) {
+		wwan_bridge->enabled = false;
+		wlan_bridge_cfg->end_lane = 14;
+	}
+	/* When the WWAN card uses 2 lanes, the WLAN card can't be used */
+	if (CONFIG(WWAN01)) {
+		wlan_bridge->enabled = false;
+		wwan_bridge_cfg->end_lane = 15;
+	}
+}
+
+void mainboard_update_devicetree_opensil(void)
+{
+	mainboard_update_mpio();
+}